隨著微電子應用的演進，複雜的元件能較高度的整合到系統晶片上，使其具有較高的速度、更多的功能與效能的增加。高速輸入輸出、矽智產與記憶體核心是高速系統晶片(High speed System-on-a-Chip; HSSOC)的三大主要元件，而高速系統晶片中有著高速輸入輸出界面將衍生出許多封裝與測試整合上的困難與挑戰。因此，在系統晶片佈局空間變得很小，提供系統的電壓值亦變小之下，封裝與測試上之信號完整度特性和失效分析對整個系統晶片發展結果的影響便十分重要。
本研究以量測技術為基礎進行球陣列封裝之信號完整性與故障非破壞分析，進而提供於高速系統晶片之應用。使用量測、建立模型與電路模擬的方法進行電氣特性與等效模型之建立，經由實際量測結果相互比較，建立適當的電子封裝等效電路模型。並進行信號完整性分析，探討球陣列封裝電子封裝電氣特性對高速數位系統晶片之影響。然後再使用一個端點開路治具加上時域反射分析儀檢視快速信號緣之時間間隔與反射電壓之參數，進行球柵陣列封裝過程的錯誤之非破壞分析。最後進行球柵陣列測試治具重複性之錯誤分析。

Microelectronic applications tend toward more complex components with higher integration at the system-on-a-chips (SoCs), higher speed, more functionality, and better performance. High speed I/Os, SIPs and memory cores are three key components in high speed SoC (HSSoC), which results in package and test integration challenges. These two issues make the package and test cost especially that related to package and test integration, one of the major costs in HSSoC development. How to increase the signal integrity of packaging and reduce the cost of high speed I/Os testing becomes an important subject so far as HSSoC development is major concerned. In order to succeed in the HSSoC products, much attention has been paid to the signal integrity (SI) and nondestructive analyses (NA) of the package interconnection. In order to succeed in the HSSoC products, much attention has been paid to the electrical model and failure analyses of the package interconnection. SI characterization and NA in the SOC package have caused significant challenges in BGA-type packaging design.
In this thesis, we propose applying a measurement technique to extracts high-speed FC-BGA packaging interconnects for signal integrity and analyze the interconnection of BGA packaging for the failure of packaging interconnections. Determining the real FC-BGA effects requires the measuring and the modeling by using TDR technique. Suitable and prompt modeling to the practical design and analysis will solve the measuring problem. HSPICE was applied to analyze the signal integrity of the package. To detect an interconnection failure in BGA packages, a nondestructive analysis system with TDR was developed. An open-end fixture (OEF) was employed to detect the rapid rise of edge signals from the package and to monitor them under the two parameters of time interval and reflection voltage. The test socket of BGA ia finally analyzed the various factors of contact effects in the production line.

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