本論文提出一個以快速傅利葉轉換(FFT)為基礎的非等頻寬濾波器組(Non-uniform Filter-bank)，能夠符合ANSI S1.11 Class-0規格的演算法，適合應用於數位助聽輔具設計。有別於過去文獻採用的平行式架構或多速率架構的濾波器組，本論文嘗試使用快速傅立葉轉換(FFT)作為核心，藉由頻域訊號的處理，將短時間的頻譜能量做調整，達到訊號的濾波效果。本架構之優點為各個子頻帶之間沒有群延遲差異，使得合成的訊號品質較佳，並且有較低的運算複雜度，相較於2013年Kuo et al.近似ANSI S1.11 Class-2規格等級的最新文獻設計，本論文提出的設計方式能減少35.8%的乘法運算和7.5%的加法運算。
在FFT Filter-bank硬體設計方面，2013年Kuo et al.最新文獻需要8個乘法器和8個加法器，並且只實現分析端的濾波器組；而本論文實現分析端與合成端的濾波器組，總共只需要3個乘法器和9個加法器，並且能減少18.5%的正規化功率消耗，即時化(Real-time)操作時脈僅需要3.32MHz。晶片實作使用TSMC 0.18um製程實現，封裝使用CQFP128作為晶片包裝，晶片的核心面積為1.4×1.4 mm2，晶片量測之總功率消耗為3.01mW@3.32MHz。

This thesis proposes an efficiently FFT-based class-0 ANSI S1.11 1/3-octave filter-banks design with the advantages of zero band group delay mismatch and low computational complexity. Compared with recent Kuo et al.’s quasi-class-2 ANSI S1.11 design, the proposed design totally has 35.8% of multiplication and 7.5% of addition reductions. In chip realization, the core size is 1.4×1.4 mm2 by using TSMC 0.18um CMOS process. The power consumption for overall ANSI S1.11 class-0 analysis and synthesis filterbank is 3.01 mW @ 3.32 MHz measured by CIC’s Agilent 93000 SoC Series. The maximum and real-time operation frequencies are, respectively, 17 and 3.32 MHz. Therefore, it would be more suitable for high-level applications of digital hearing aids in the future.

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