成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	莊堯仁 Chuang, Yao-Jen
論文名稱：	採用新式泡沫容忍編碼器之1 GHz六位元快閃式類比數位轉換器 A 1G Sample/s 6-bit Flash A/D Converter with Novel Bubble Tolerant Thermometer-to-Binary Encoder
指導教授：	劉濱達 Liu, Bin-Da
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	88
中文關鍵詞：	泡沫、快閃式類比數位轉換器、溫度計碼轉二位元碼編碼器
外文關鍵詞：	Thermometer-to-binary encoder, Flash A/D converter, Bubble
相關次數：	點閱：70 下載：2
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

　　近年來隨著製程的進步，混合訊號的設計已是一個必然的趨勢。而在混合訊號的設計中，類比數位轉換器一直扮演著一個很重要的角色。一個好的類比數位轉換器可以有效地提升整體晶片的效能。
　　
　　在本論文中，我們提出了一個可操作在1 GHz工作頻率的六位元快閃式類比數位轉換器。首先我們針對溫度計碼與二位元碼之間轉換過程中因為泡沫效應所可能造成的編碼錯誤作一分析與討論，並提出一個新式可容忍泡沫的編碼器。此編碼器採用分段編碼的方式，針對每一個二位元碼進行與相關溫度計碼的個別對應編碼。因此泡沫效應只會反應在較低的位元碼上，進而達到對泡沫效應壓抑的效果；而模擬結果也顯示所提出的編碼器可以有效地壓抑泡沫效應所造成的編碼錯誤。
　　
　　此外，我們也針對各個類比數位轉換器子電路的電路實現與設計提出討論，包含了取樣電路、比較器、以及誤差平均網路等。並在台積電0.18微米一層多晶矽六層金屬之互補式金氧半製程中，以1.8伏特供應電壓的條件下完成設計的模擬以及驗證。當輸入訊號為324 MHz以及取樣頻率為1 GHz時，所設計的快閃式類比數位轉換器可以得到約36.45 dB的訊號對雜訊及諧波失真比，相當於5.76個有效位元。整體電路的功率消耗為186 mW。

　　With the relentless advancement of process technology, mixed-signal circuit design has become an inevitable trend for system integration. Behaving as an interfacing bridge between digital and analog realms, A/D converter always plays a critical role. A high performance A/D converter can effectively improve the whole circuit performance.
　　
　　In this thesis, a 1 GHz 6-bit flash A/D converter is proposed. The main topic is focused on resolving coding errors induced by the bubble effect of thermometer-to-binary encoder. For addressing this issue we propose a novel bubble tolerant thermometer-to-binary encoder. In this design, each bit is encoded respectively according to the corresponding bits of thermometer code. Therefore the bubble effect can only reflect itself on the lower significant bits and thus the bubble-induced coding error can be suppressed.
　　
　　A 1GHz 6-bit flash A/D converter prototype has been designed for the verification of proposed encoder. Building blocks such as track-and-hold circuit, comparator, and offset-averaging network are discussed. The whole circuit is simulated and verified by using TSMC 0.18 μm 1P6M CMOS process spice model. Simulation results show the SNDR value for the proposed flash A/D converter is about 36.45 dB, equaling to 5.76 bits ENOB, under 324 MHz input signal and 1 GHz sampling rate. The total power consumption is 186 mW.

Chapter 1　Introduction ---------------------------------------  1
　1.1　Motivation ---------------------------------------------  1
　1.2　Organization for the Thesis ----------------------------  3
Chapter 2 Fundamentals of A/D Converter -----------------------  5
　2.1　Introduction -------------------------------------------  5
　2.2　Basic Concepts -----------------------------------------  6
　　2.2.1　Introduction of A/D Converters ---------------------  6
　　2.2.2　Aliasing Effect ------------------------------------  7
　　2.2.3　Ideal A/D Converter --------------------------------  8
　　2.2.4　Quantization Error ---------------------------------  9
　2.3　Specifications ----------------------------------------- 12
　　2.3.1　Static Specifications ------------------------------ 12
　　2.3.2　Dynamic Specifications ----------------------------- 15
　2.4　Flash A/D Converter ------------------------------------ 17
Chapter 3　Bubble Tolerant Encoders for Flash A/D Converter --- 19
　3.1　Introduction ------------------------------------------- 19
　3.2　Bubble Effect ------------------------------------------ 20
　3.3　Conventional Binary ROM-Based Encoder ------------------ 21
　　3.3.1　Circuit Functionality ------------------------------ 21
　　3.3.2　Encoding Scheme ------------------------------------ 23
　3.4　Wallace Tree Encoder ----------------------------------- 25
　3.5　Gray Encoder ------------------------------------------- 26
　　3.5.1　Gray ROM-Based Encoder ----------------------------- 27
　　3.5.2　Fully Digital Gray Encoder ------------------------- 29
　3.6　Proposed Encoder --------------------------------------- 33
　　3.6.1　Introduction --------------------------------------- 33
　　3.6.2　Encoding Scheme ------------------------------------ 36
　　3.6.3　Simulation Results --------------------------------- 41
　　3.6.4　Circuit Implementation ----------------------------- 43
Chapter 4　Building Blocks Design and Simulation Results ------ 47
　4.1　Track-and-Hold Circuit --------------------------------- 47
　　4.1.1　Circuit Implementation ----------------------------- 49
　　4.1.2　Simulation Results --------------------------------- 50
　4.2　Comparator Design -------------------------------------- 50
　　4.2.1　Bias Circuit --------------------------------------- 51
　　4.2.2　Preamplifier --------------------------------------- 53
　　4.2.3　Latch Comparator ----------------------------------- 56
　4.3　Offset-Averaging Technique ----------------------------- 63
　4.4　Clock Buffer ------------------------------------------- 70
　4.5　Encoder ------------------------------------------------ 71
　4.6　Circuit Layout ----------------------------------------- 72
　4.7　Simulation Results ------------------------------------- 74
　　4.7.1　Static Performances -------------------------------- 74
　　4.7.2　Dynamic Performances ------------------------------- 76
　　4.7.3　Relative Power Consumption ------------------------- 80
　　4.7.4　Post-Layout Simulation Results --------------------- 81
　4.8　Comparison --------------------------------------------- 82
Chapter 5　Conclusions and Future Work ------------------------ 83
　5.1　Conclusions -------------------------------------------- 83
　5.2　Future Work -------------------------------------------- 84
References ---------------------------------------------------- 86
                                    

[1]　M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1847–1858, Dec. 2001.
[2]　S. Tsukamoto, W.G. Schofield, and T. Endo, “A CMOS 6-b, 400-MSample/s ADC with error correction,” IEEE J. Solid-State Circuits, vol. 33, pp. 1939–1947, Dec. 1998.
[3]　K. Uyttenhove and M. S. J. Steyaert, “A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS,” IEEE J. Solid-State Circuits, vol. 38, pp. 1115–1122, July 2003.
[4]　G. Geelen, “A 6 b 1.1 GSample/s CMOS A/D converter,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 128–129, 438.
[5]　P. C. S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination,” IEEE J. Solid-State Circuits, vol. 37, pp. 1599–1609, Dec. 2002.
[6]　X. Jiang and M.-C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuits, vol. 40, pp. 532–535, Feb. 2005.
[7]　B. Razavi, Principle of Data Conversion System Design. New York: Wiley 1995.
[8]　Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, and H. Ikawa, “A 400MSPS 8b flash AD conversion LSI,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1987, pp. 98–99.
[9]　P. M. Figueiredo and J. C. Vital, “Termination of averaging networks in flash ADCs,” in Proc. 2004 Int. Symp. Circuits and Systs., vol. 1, May 2004, pp. 121–124.
[10]　E. Sall, M. Vesterbacka, and K. O. Andersson, “A study of digital decoders in flash analog-to-digital converters,” in Proc. 2004 Int. Symp. Circuits and Systs., vol 1, May 2004, pp. 129–132.
[11]　D. G. Knierim, “Error tolerant thermometer-to-binary encoder,” U.S. Patent 4586025, Apr. 29, 1986.
[12]　R. Kanan, F. Kaess, and M. Declercq, “A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder,” in Proc. 1999 Int. Symp. Circuits and Systs., vol. 2, June 1999, pp. 420–423.
[13]　D. G. Knierim, “Thermometer-to-adjacent bindary encoder,” U.S. Patent 4733220, Mar. 22, 1988.
[14]　L. Daegyu, Y. Jincheol, C. Kyusun, and J. Ghaznavi, “Fat tree encoder design for ultra-high speed flash A/D converters,” in Proc. 2002 Midwest Symp. Circuits and Systs., vol. 2, Aug. 2002, pp. 87–90.
[15]　M. Steyaert, R. Roovers, and J. Craninckx, “A 100 MHz 8 bit CMOS interpolating A/D converter” in Proc. IEEE Cust. Int. Circuits Conf., May 1993, pp. 28.1.1–28.1.4.
[16]　Y. Gendai, Y. Komatsu, S. Hirase, and M. Kawata, “An 8b 500MHz ADC,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1991, pp. 172, 311.
[17]　M. Ito, T. Miki, S. Hosotani, T. Kumamoto, Y. Yamashita, M. Kijima, T. Okuda, and K Okada, “A 10 bit 20 MS/s 3 V supply CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 29, pp. 1531–1536, Dec. 1994.
[18]　S. Padoan, A. Boni, C. Morandi, and F. Venturi, “A novel coding scheme for the ROM of parallel ADCs, featuring reduced conversion noise in the case of single bubbles in the thermometer code,” in Proc. Int. Conf. Electron. Circuits and Systs., vol. 2, Sept. 1998, pp. 271–274.
[19]　J. van Valburg and R. van de Plassche, “An 8 b 650 MHz folding ADC,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1992, pp. 30–31, 234.
[20]　O. Carnu and A. Leuciuc, “Optimal offset averaging for flash and folding A/D converters,” in Proc. 2004 Int. Symp. Circuits and Systs., vol. 1, May 2004, pp. 133–136.
[21]　P. E. Allen and D.R Hoolberg, CMOS Analog Circuit Design. New York: Oxford, 2002.
[22]　D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley 1997.
[23]　M. Gustavsson, J. J. Wikner, and N. N. Tan, CMOS Data Converters for Communications. Boston, MA: Kluwer Academic 2000.
[24]　M. J. M. Pelgrom, H. P. Tuinhout, and M. Vertregt, “Transistor matching in analog CMOS applications,” in IEEE Int. Electron Devices Meeting Dig. Tech. Papers, Dec. 1998, pp. 915–918.
[25]　R. H. Walden, “Analog-to-digital converter technology comparison,” in Proc. GaAs IC Symp. Dig. Tech., Oct. 1994, pp. 217–219.

校內：2006-08-22公開
校外：2006-08-22公開

簡易檢索 / 詳目顯示

相關論文