本論文為提出應用於2.4/24 GHz雙頻接收機前端電路之子電路設計，其中可分為兩個部分:第一部分為2.4及24 GHz接收機前端電路設計；第二部分為2.4 GHz非整數型鎖相迴路電路設計。這些電路操作電壓皆為1.8 V，且使用TSMC 0.18 μm CMOS製程實現。
2.4 GHz接收機前端電路主要電路架構為一級疊接組態低雜訊放大器串接摺疊疊接式(folded-cascode)混頻器。第一級疊接組態低雜訊放大器擁有較低的雜訊指數，以便同時降低後級電路所提供之雜訊指數，增加整體接收機靈敏度。第二級為折疊疊接式混頻器係採用多閘級電晶體線性技術使整體接收機線性度提升。24 GHz接收機前端電路主要電路架構為三級低雜訊放大器串接一級電流再利用注入式混頻器。透過三級放大器可同時達到低雜訊指數及高轉換增益效果，而第二級電流再利用注入式混頻器可提供較高的轉換效率與轉換增益。2.4 GHz接收機前端電路將2.4 GHz的輸入訊號調變降頻為200 MHz輸出訊號。其量測結果顯示，整體轉換增益為18.295 dB；雜訊指數為6.01 dB；P1dB為-26 dBm；IIP3為-15 dBm；功率消耗為60.1 mW。24 GHz接收機前端電路將24 GHz的輸入訊號調變降頻為2.4 GHz輸出訊號。其量測結果顯示，整體轉換增益為18.7 dB；雜訊指數為9.6 dB；P1dB為-26 dBm；IIP3為-15 dBm；功率消耗為40.5 mW。
2.4 GHz非整數型鎖相迴路中，包含相頻偵測器(PFD)、充電泵(CP)、迴路濾波器(LPF)、壓控振盪器(VCO)、多模數除頻器(MMD)及三角積分調變器。模擬之參考頻率為18.75 MHz，而鎖相迴路提供2.4 GHz至2.521875 GHz的本地振盪訊號。在鎖相迴路量測上，量測之參考頻率為19 MHz，其操作頻率為2.432 GHz至2.555 GHz；相位雜訊在頻率偏移10 MHz處為-114.65 dBc/Hz；輸出功率皆大於-10 dBm；功率消耗為23 mW。

The thesis provides the subcircuit designs of 2.4/24 GHz RF receiver front-end circuits, which is applicable for a switchable dual-band sensor receiver. This thesis contains two parts. The first part concerns the design of the 2.4 and 24 GHz RF receiver front-end circuits. The design of 2.4 GHz Fractional-N PLL is described in the second part. All the above-mentioned designs are powered by 1.8 V and fabricated in TSMC 0.18 μm CMOS process.
The circuit structure of the 2.4 GHz RF receiver front-end circuits is composed of one stage of cascode LNA and a folded cascode mixer. The first stage cascode LNA provides lower noise figure (NF), to reduce the NF effect provided by the subsequent circuit, and thus to increase the overall receiver sensitivity. The second stage folded cascode mixer adopts multiple gated transistor (MGTR) linear technology to improve the overall receiver linearity. The circuit structure of the 24 GHz RF receiver front-end circuits is composed of three stages LNA and a current-reused bleeding mixer. The three stages LNA can simultaneously achieve low noise and high conversion gain. The second stage current-reused bleeding mixer can provide higher conversion efficiency and conversion gain. The 2.4 GHz RF receiver front-end circuit down-converts 2.4 GHz input signal to 200 MHz at the ouput port. The measured conversion gain is 18.295 dB and noise figure is 6.01 dB. The measured P1dB is -26 dBm and IIP3 is -15 dBm. The circuit consumes 60.1 mW. The 24 GHz RF receiver front-end circuit down-converts 24 GHz input signal to 2.4 GHz at the ouput port. The measured conversion gain is 18.7 dB and noise figure is 9.6 dB. The measured P1dB is -26 dBm and IIP3 is -15 dBm. The circuit consumes 40.5 mW.
The 2.4 GHz fractional-N PLL, in which the target reference frquecny is 18.75 MHz, includes a phase frequency detector, a charge pump, a low pass filter, a voltage-controlled oscillator, a multi-modulus divider and a delta-sigma modulator. The PLL frequency tuning range is from 2.4 GHz to 2.521875 GHz. When the PLL’s reference frequency is 19 MHz, frquency tuning range from 2.432 GHz to 2.555GHz, the measured phase noise is -114.65 dBc/Hz at 10 MHz offset frequency, the output power is above -10 dBm. The total power consumption of PLL is 23 mW.

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