H.264是一個應用在多媒體視訊上的一個壓縮標準，其編碼效能比起之前的視訊標準有明顯的進步，在針對殘值的編碼上，採用了內容適應性可變長度編碼，其編碼方式除了擁有一般可變長度編碼的特性之外，更依據內容的不同而使用不同的不等長碼表，以便能更加壓縮空間上、統計上的多餘資訊，達到更好的壓縮效能，使其壓縮效能接近算數編碼而複雜度卻遠低於算數編碼。
本論文提出一種針對H.264中內容適應性可變長度解碼器的積體電路架構設計，並針對編碼的特性去進行統計及分析，在增加少量資料路徑的情形之下設計一個高效率的多參數的解碼器，在其他方面，則試著利用數學邏輯運算的方式，簡化解碼器的硬體成本。所在本文中所提出的內容適應性解碼器能達到及時解壓縮高畫質影片的要求。

H.264 is a brand new compression standard for multimedia communication and storage. The compression performance is much better than other conventional standards. Context-based variable length coding is used in H.264 for the encoding of residual coefficients. CAVLC selects different VLC tables adaptively according to the video contents. Better compression ratio is achieved by removing statistical redundancy with the aid of spatial correlation. CAVLC performs almost as well as the arithmetic coding but possesses less computational complexity.
In this thesis, we propose a VLSI architecture for H.264 CAVLC decoder. We have designed a highly efficient multi-symbol decoder with high decoding throughput by ultilizing the properties of CAVLC. On the other hand, the arithmetic operations were used to reduce the hardware cost of decoding. The design proposed in the thesis can meet the real time requirement for HD video decoding.

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