本研究針對電阻抗影像系統中設計多通道之可調變電流產生器，其中電阻抗影像系統是利用組織的阻抗特性，由外部加入多通道的交流電流，並量測其電壓值，經過影像重建的演算法，即可得到一截面阻抗影像。而電阻抗影像系統中，注入電流的電流產生器扮演非常重要的角色，電流產生器有兩個重要的特性：（1）輸出的電流必須穩定不受負載效應的影響，（2）各通道的電流產生器必須有相同的電特性。在過去的研究，電路是以電子電路的個別元件所組成，體積龐大，且需花費時間做微調，來達到各個通道的電流產生器特性一致之要求。因此，本研究主要以VLSI的技術，實現多通道的電流產生器於單一晶片上，以期特性之一致。就單一電流產生器而言，電路架構包含了兩個部分，分別是電壓控制電流源和數位類比轉換器；其中電壓控制電流源由三個運算放大器構成一負回授穩流電路，使輸出電流不受到負載效應的影響；數位類比轉換器將由數位振盪器所提供的載波，轉換成電壓控制電流源所需要的交流電壓，且透過數位輸入得到不同大小振幅的電壓。多通道之電流源係共用一個數位類比轉換器，因此架構上每組電壓控制電流源使用類比儲能元件和類比乘法器，以達成多通道電流產生器於單一晶片之設計。最後使用Hspice進行電路分析，並依據台積電(TSMC) 0.25μm CMOS 之製程參數來驗證個別電路之可行性。

In this study, the multi-channel current generators are designed and developed for bio-impedance system. According to the characteristics of tissue impedance, through injecting AC currents from periphery, and then measuring voltages, the impedance image of tissue can be obtained using image reconstruction algorithm. There are two major properties of current generator: (1) the amplitude of the current generator must be stable without significant loading effect; (2) the property of each current generator must be as similar as possible. In past study, the current generator is made of discrete components. The disadvantage of the traditional analog device is the imprecision of the values of resistances and capacitors. It needs to be fine-tuned to assure the channels with same specification. It is also big in volume. The purpose of the study is to design a multi-channel programmable current generators in ASIC. For single channel, the system consists of voltage controlled current source (VCCS) and digital to analog converter (DAC). The VCCS with feedback network is used to make current stable. The DAC converts the carrier provided from digital oscillator to AC voltage for VCCS. Its amplitude is set by digital input. For the multi-channel current generators, the DAC must be shared with every channel VCCS. It needs to add an analog storage and analog multiplier. In this study, all of the functional blocks have been verified by using Hspice based on the parameters of TSMC 0.25μm CMOS process.

[1] A. Wald, “Electrical safety in Medicine” in Handbook of bioengineering, New York: McGraw-Hill, pp34.1-34.20, 1987.
[2] A. Pellegrini, A.Gnudi, and G. Baccarani, “CMOS analog multipliers based on a class-B squaring circuit,” Proc. of The IEEE International Symposium on Circuits and Systems, Vol. 1 , pp. 245 -248, June 1998.
[3] Abdulkerim L. Coban and Phillip E. Allen, “A 1.5V four-quadrant analog multiplier,” Proc. of the 37th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 117 -120 Aug. 1994.
[4] Akira Hyogo, Yoshio Fukutomi, and Keitaro Sekine, “Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair,” Proc. The IEEE International Symposium on Circuits and Systems, Vol.2, pp. 274 -277, June 1999.
[5] Behzad Razavi, Principles of Data Conversion System Design, John Wiley & Sons Inc., 1995.
[6] Bogdan M. and Wilamowski, “VLSI analog multiplier/divider circuit,” Proc. IEEE International Symposium on Industrial Electronics, Vol. 2, pp. 493 -496, July 1998.
[7] C. M. Hammerschmied and Q. Huang, “Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD,” IEEE J. Solid-State Circuits, vol.33, NO.8, pp. 1148-1157, Aug. 1998.
[8] D. J. Nowicki and J. G. Webster, “A one op-amp current source for electrical impedance tomography,” Proc. Annual Int. Conf. IEEE Eng. Med. & Biol. Soc., pp. 457-458, 1989.
[9] D. Patranabis and D. Ghosh, “A four quadrant multiplier with independent control of range and sensitivity,” IEEE Trans. Instrum. Meas., vol. 38, no.1, pp. 17-21, Feb. 1989.
[10] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons Inc., 1997.
[11] David C. Soo and Robert G. Meyer, “A four-quadrant NMOS analog multiplier,” IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp.1174-1178, Dec. 1982.
[12] Fu-Hsing Wu, Electrical Impedance Image Reconstruction Using DSP, Master Thesis, Institute of Biomedical Engineering, National Cheng Kung University, July 1998.
[13] G. A. Hadgis and P. R. Mukund, “A novel CMOS monolithic analog multiplier with wide input dynamic range,” IEEE VLSI Circuits Dig. Tech. Conf., pp. 310-314, Jan. 1995.
[14] Ganesh K. Blachandran and Phillip E. Allen, “Switched-current circuits in digital CMOS technology with low charge-injection errors,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp.1271-1281, Oct. 2002.
[15] G. Moon, M. E. Zaghloul, and R. W. Newcomb, “An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range,” IEEE Trans. Circuits and Systems., vol.37, no. 10, pp.1284-1288, Oct. 1990.
[16] Hong-wei Wang, Cheong-fat Chan, and Chiu-sing Choy, “High speed CMOS digital-to-analog converter with linear interpolator,” IEEE Trans. Cons. Electron., vol. 46, no. 4, nov. 2000.
[17] J. G. Webster, Electrical Impedance Tomography, Adam Hilger, 1990.
[18] K. Bult and G. J. M. Gleen, “An inherently linear and compact MOST-only current division technique,” IEEE J. Solid-State Circuits, vol.27, pp. 1730-1735, Dec. 1992.
[19] K. R. Stafford, P. R. Gray, and R. A. Blanchard, “A complete monolithic sample/hold amplifier,” IEEE J. Solid-State Circuits, vol. SC-9, no.6, pp. 381-387, Dec. 1974.
[20] L. Wang, Y. Fukatsu, and K. Watnabe, “Characterization of current-mode CMOS R-2R ladder digital-to-analog converters,” IEEE Trans. Instrum. Meas., vol. 50, no.6, pp. 1781-1786, Dec. 2001.
[21] Liang Dai and Harjani R., “CMOS switched-opamp based sample-and-hold circuit,” IEEE J. Solid-State Circuits , Vol. 35, No. 1 , pp. 109 -113, Jan. 2000.
[22] M. Ehlert and H. Klar, “A 12-bit medium-time analog storage device in a CMOS standard process,” IEEE J. Solid-State Circuits, Vol. 33, No. 7, pp.1139-1143, July 1998.
[23] N. Saxena and J. J. Clark, “A four-quadrant CMOS analog multiplier for analog neural networks,” IEEE J. Solid-State Circuits, vol. 29, no. 6, June 1994.
[24] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, edition, Oxford University Press, 2002.
[25] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, edition, John Wiley & Sons Inc., 2001.
[26] T.-L. Lin, The Application of The Electrical Impedance Tomography to Gastric Emptying, Master Thesis, Institute of Biomedical Engineering, National Cheng Kung University, June 2001.
[27] W. B. Wilson, H. Z. Massoud, E. J. Swanson, R. T. George, and R. B. Fair, “Measurement and modeling of charge feedthrough in n-channel MOS analog switches,” IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1206-1213, Dec. 1985.
[28] Yi-Yu Lu, The Electrical Impedance Imaging System: A Digital Design Approach, Master Thesis, Institute of Biomedical Engineering, National Cheng Kung University, June 1995.