本論文主要以ARM指令級架構建構一暫存器轉移層級(RTL)之高速處理器。在RTL層級設計中，以十三級管線化的架構實現高速處理器，並附加上危障前饋處理以及跳躍預測。為了要驗證處理器的完整性以及正確性，執行程式便是一最佳手段。但由於程式特性的緣故，一般程式僅能驗證到處理器的基本功能，許多進階的功能則無法被印證。作業系統特性不僅能驗證基本的功能，而且也能包含驗證進階功能的部分，而達到完整的功能驗證。

本論文採用實驗室先前以SystemC完成的Multi-core Virtual Platform作為實驗之驗證平台，並借由Modesim提供協同模擬環境，達成全系統階級模擬驗證。以Linux kernel 2.6.38.7做為開機使用的作業系統，合成過後的處理器可以達到333MHz的執行速度。在執行效能方面，以完美的快取模型以及加入跳躍預測機值及資料危障處理，IPC最佳表現有高達0.2844。

This thesis is mainly about building a high-speed processor with register transfer level (RTL) under ARM instruction set architecture. In terms of register-transfer level design, this processor is implemented with a 13-stage pipeline architecture along with a forwarding unit and a branch predictor. The best way to verify the integrality and correctness of the processor is through running programs. However, due to the characteristics of normal programs, they can verify only the basic functions of the processor, and leaving many advanced functions unverified. The characteristics of general operating systems will not only verify the basic functions but also the advanced functions of the processor, and therefore achieves full-function verification.

This thesis adopts Multi-core Virtual Platform which is finished with SystemC level for full-system simulation and verification in Modelsim Co-Sim environment. This platform takes Linux kernel 2.6.38.7 for operating system and achieves about 333MHz executing rate in post-synthesis simulation. By adding branch predictor and forwarding unit into CPU architecture with perfect cache model, the performance of IPC reaches up to 0.2844.

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