本篇論文提出一個低成本及可快速訓練的自動語者語音辨識系統晶片設計，利用低成本及可快速訓練的特性使得自動語者語音辨識系統在現實應用中是具效益且可負擔的。本設計分為四個部分，分別為：特徵擷取模組、語者模型訓練模組、語者辨識模組以及語音辨識模組。
特徵擷取模組採用線性預估倒頻譜係數(Linear Prediction Cepstal Coefficients)作為語者發聲之特徵。語音辨識部分使用動態時間校準來判別目標語音。語者模型訓練部分則提出二元對分分類法 (Binary Halved Clustering Method) 產生語者模型，利用二元對分分裂的規律性降低運算複雜度，進而節省52%晶片面積，降低68%反應時間，並達到90%的辨識率，有效實現低成本需求的晶片硬體設計。
我們利用晶片設計製作中心(Chip Implementation Center, CIC )與台灣積體電路公司(TSMC)所提供的90奈米製程梯次(TN90GUTM-103B)完成本晶片實作下線(Tape-Out)。晶片面積為1.47*1.47 mm2，以84支接腳封裝，閘總數(Gate Count)約為395000，消耗功率為8.74 mW，工作頻率為50MHz，取樣頻率為16kHz。

This study proposed a low-cost and fast-trainable chip design for automatic speaker-speech recognition (ASSR) system. There are four parts of this proposed system, which is including: feature extraction module, speaker model training module, speaker recognition module, and speech recognition module.
LPCC (Linear Predictive Cepstral Coefficients) is adopted into the proposed feature extraction module. The speech recognition uses dynamic time warping (DTW) to classify the target speech. The novel binary halved clustering (BHC) method uses binary-halved splitting to generate speaker models for low complexity requirement. Compared with the conventional works, simulation results indicate that the proposed hardware accelerator achieves 52% less cost, 68% less responding time, an ASSR accuracy of 90%. This ASSR system to efficiently implement the low cost chip design.
This study has been taped-out in TSMC’s 90nm process. The chip area is 1.47*1.47 mm2, 84-pin package, gate count is 395K, and the power dissipation is 8.74 mW. The operation frequency is 50 MHz, while the Sampling rate is 16 kHz.

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