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研究生： 王嘉德
Wang, Chia-te
論文名稱： 電子系統層級上之基礎測試平台架構
A Framework for Electronic System Level (ESL) Test Platform
指導教授： 李昆忠
Lee, Kuen-jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 62
中文關鍵詞： 電子系統層級 、測試平台 、事務級模型
外文關鍵詞： ESL, IEEE 1500, SystemC, TLM, test platform, IEEE 1149.1
相關次數： 點閱：68  下載：4 
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    • 隨著今日系統晶片複雜度的提升，系統設計以暫存器傳輸層級為基礎的驗證方式變的缺乏效率且耗費大量的時間。因此電子系統層級的設計方法逐漸成為開發系統晶片的趨勢。全球的IC設計大廠也漸漸採用事務級模型為主的發展平台開發他們的系統晶片產品。藉由將他們的系統從電子系統層級逐步優化到產品，可以大幅降低新產品的上市時間。由於測試一直是伴隨在發展好的暫存器傳輸層級設計之後，因此要在暫存器傳輸層級上優化一個系統的測試成本同時也是一個耗費大量的時間的過程，因此我們以虛擬平台技術發展了一個電子系統層級上的測試平台。 憑藉虛擬原型高速模擬的特性，系統發展者可以採用比過去更快的方式分析與決定系統中需要的共同測試硬體和不同的系統組態。如同CoWare的做法, 我們也提供了測式存取機制控制器傳輸層級模組的虛擬原型給不同的系統開發者並且達到在電子系統層級上矽智產重複使用的目標。因此系統開發者可以快速地組裝虛擬測試平台同時不需花費心力去開發系統中的測試原件。

    With the increasing complexity of today’s SoC, RTL-based simulations become inefficient and very time consuming for verifying system designs. Therefore, ESL-based design methodology is becoming the trend for an SoC development. TLM platforms are adopted dramatically by big IC design companies in the world for developing their SoC products. Through refining their systems from ESL toward implementations, they can shorten time to market for new products. Since testing always follows well developed RTL designs, refining test cost of an SoC at RTL is also a time consuming process, therefore we developed an ESL test platform framework based on the virtual platform technology. With the high simulation speed characteristic of virtual prototypes, system designer can decide and analyze proper test infrastructure with different system configurations in their system in a rapider way than ever go. Like CoWare, we also provide TLM TAM controller, a virtual prototype, for other system designers and reach the goal of IP reuse at ESL. So system designers can assemble a virtual test platform quickly and take no effort on developing test components in their systems.

    Chapter 1 Introduction.......................................P1 1.1 Motivation....................................................P1 1.2 Overview of Thesis......................................P2 1.3 Organization of Thesis.................................P3 Chapter 2 Backgrounds......................................P4 2.1 IEEE Standards............................................P4 2.1.1 IEEE Std. 1666.........................................P4 2.1.2 IEEE Std. 1500.........................................P7 2.2 Previous Works...........................................P9 2.2.1 SoC Test Platform.....................................P9 2.2.1.1 Software.................................................P9 2.2.1.2 Hardware................................................P9 2.2.1.3 Test Procedures......................................P10 2.2.1.3.1 Software-based Test Flow...................P10 2.2.1.3.2 Hardware-based Test Flow..................P10 2.2.2 Memory BIST...........................................P11 2.2.2.1 Encoding Scheme...................................P11 2.2.2.2 March Integration...................................P11 Chapter 3 SystemC TL Models..........................P13 3.1 IEEE 1500 Wrapper.....................................P13 3.2 Virtual Wrapped Core..................................P15 3.3 TAM Controller.............................................P16 3.3.1 Data Granularity: Application-packet.........P16 3.3.2 AMBA AHB Wrapper................................P17 3.3.3 Data Granularity: Bus-packet......................P18 3.3.3.1 Timing Accuracy: Cycle-accurate............P18 3.3.3.2 Timing Accuracy: Approximately-timed..P19 3.4 Test Bus...........................................................P20 3.4.1 TAP Controller.............................................P20 3.5 Memory BIST.................................................P21 Chapter 4 New TAM Controller Architecture.......P23 4.1 Architecture II.................................................P24 4.2 Hardware Components....................................P25 4.2.1 Memory Access Unit....................................P25 4.2.1.1 Entry of Queue.........................................P26 4.2.2 Buffer Hierarchy..........................................P27 4.2.3 TMS Generator............................................P28 4.2.4 Comparator.................................................P29 4.2.5 Control Unit.................................................P30 4.2.5.1 Configuration............................................P30 4.2.5.2 Ready Signals............................................P31 4.2.5.3 Shift Signals..............................................P31 4.2.5.3.1 Counters................................................P32 4.2.5.4 Halt Operation..........................................P34 Chapter 5 ESL Test Platform................................P35 5.1 Cycle-accurate ESL Test Platform..................P35 5.2 Approximately-timed ESL Test Platform.......P37 5.3 Software..........................................................P38 5.3.1 Test Program................................................P38 5.3.2 Test Data......................................................P38 5.4 Automation Tool.............................................P39 5.4.1 Wrapper Synthesizer....................................P39 5.4.2 Pattern Transformer.....................................P40 5.5 IP Reuse..........................................................P41 Chapter 6 Estimates..............................................P43 6.1 Estimate # of Cores in Parallel Test...............P43 6.1.1 Architecture I..............................................P43 6.1.1 Architecture II.............................................P44 6.2 Test Time Estimate.........................................P45 6.3 Bus Utilization................................................P46 Chapter 7 Experimental Results...........................P48 7.1 Simulation Time.............................................P48 7.2 Test Time........................................................P49 7.3 Test Data........................................................P49 7.4 Case Study I...................................................P50 7.4.1 Waveform....................................................P50 7.4.2 Bus Utilization.............................................P52 7.5 Case Study II..................................................P54 7.6 Case Study III.................................................P55 Chapter 8 Conclusions..........................................P59 References

    [1] EETimes: http://www.eetimes.com, 2004
    [2] SOCentral: http://www.soccentral.com, 2006
    [3] Ming-Long Wu, Performance Analysis and Enhancement of SOC Test Platforms, 2005
    [4] Sheng-Chih Shen, A Low Cost Memory Built-in Self-Test Architecture and its Design Automation, 2005
    [5] Frank Ghenassia , Transaction level modeling with SystemC :TLM concepts and applications for embedded systems, Springer, 2005.
    [6] CoWare’s manuals, 2006
    [7] David C. Black and Jack Donovan, SystemC :from the ground up, Springer, 2004.
    [8] T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer Academic Publishers, 2002.
    [9] P.R. Panda, ”SystemC - a modeling platform supporting multiple design abstractions” in Proc. 14th International Symp., 2001, pp.75 – 80.
    [10] W.R. Davis, “Getting high-performance silicon from system-level design” in Proc. IEEE Computer Society Annual Symp., Feb. 2003, pp.238 – 243.
    [11] A. Sayinta, G. Canverdi, M. Pauwels, A. Alshawa, W. Dehaene, “A mixed abstraction level co-simulation case study using SystemC for system on chip verification” Design, Automation and Test in Europe Conference and Exhibition, 2003, pp.95 - 100.

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