隨著摩爾定律的推進，尺寸的微縮是現今積體電路產業中的一大挑戰，當尺寸不斷微縮時，短通道效應會越發顯著。然而目前金屬氧化物半導體場效電晶體已經由平面型發展至多閘極結構，此一發展能夠增加閘極控制力並且有效抑制短通道效應。而鰭式場效應電晶體是目前最被廣泛使用的元件，而在五奈米節點，鰭式場效應電晶體開始無法克服微縮所遇到的難題，因而需要閘極控制力更強的元件，因此發展出了許多結構，包括環繞式閘極、奈米薄片、奈米線電晶體都是目前能夠抑制短通道效應的方法。
由於奈米片電晶體的閘極在通道的包覆面積較大，閘極控制力提升，能夠優化電晶體特性。然而奈米片電晶體的最大電場會發生在通道的四個角落，電場增加會導致閘極誘導汲極洩漏電流增加，使元件在關閉狀態時會產生更大的漏電，進而產生功率消耗。
在本篇論文中，我們利用Sentaurus TCAD模擬出由IRDS提供的五奈米節點的奈米片電晶體，並比較在有無內部側壁絕緣層時的特性差異，並針對不同的內部側壁絕緣層厚度進行探討，並討論側壁絕緣層材料差異及長度對閘極誘導汲極洩漏電流造成的影響，使元件能夠優化。

With the advancement of Moore's Law, dimension scaling is a major challenge in the integrated circuit industry for decades. As the dimension continues to shrink, the short-channel effect will become more pronounced. However, the metal oxide semiconductor field effect transistors (MOSFET) have been developed from a planar type to a multi-gate structure. The development can increase the gate control and effectively suppress the short-channel effect. FINFET is generally the most widely used device. However, at sub-5nm technology node, FINFET is unable to overcome the difficulties encountered in scaling. Therefore, it requires a stronger gate control device. That is why many structures have emerged, including gate-all-around MOSFETs, nanosheets FETs, and nanowire FETs, which are the methods to suppress the short-channel effect currently.
Since the gate of the nanosheet FETs has a larger covering area in the channel, the gate control can be improved, and the characteristics of the transistor can be optimized. However, the maximum electric field of the nanosheet FETs will occur in the four corners of the channel. The increase of the electric field will increase the gate-induced drain leakage current, which will cause greater leakage when the device is in the off-state, thereby generating power consumption.
In this paper, we use Sentaurus TCAD to simulate nanosheet FETs for 5nm technology node in IRDS roadmap, and compare the difference in electrical characteristics with the inner spacer or without the inner spacer, and perform the calculation for different thicknesses of the inner spacer. We discuss the difference of material and length of the inner spacer on the gate-induced drain leakage current, so that the device can be optimized.

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