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研究生：	許世勳 Hsu, Shih-Hsun
論文名稱：	單晶片網路系統路由器之設計與實現 Design and Implementation of a Router for Network-on-Chip
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	102
中文關鍵詞：	路由器、單晶片網路、蟲洞、虛擬通道、管線化
外文關鍵詞：	NoC, router, wormhole, virtual channel, pipeline
相關次數：	點閱：106 下載：1
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　　設計一個複雜的單晶片系統(SoC)將會遇到許多挑戰，例如矽智財(Silicon IP)的整合和重複使用(resuibility)以及系統的可擴充性。而單晶片網路系統(NoC)可以有效解決之。本單晶片網路系統(aNoC)是一組由晶片網路(on-chip network)連接的數個適應性處理器核心所組成的系統平臺(template)，而使用晶片網路的架構可以去除匯流排架構所造成的擴充性問題。

　　然而，經由網路繞送資料的做法也會產生頻寬、傳遞沿遲、面積增加、和功率消耗等等代價。本篇論文包含aNoC平臺晶片網路的設計論點，以及NoC平臺晶片網路上的路由器設計與實現。該路由器利用一種新型的切換演算法來達成最大的通道使用率，並且該路由器的路由模組可以根據不同的路由演算法任意的抽換。而該路由器採用蟲洞(wormhole)、虛擬通道(virtual channel)和管線化(pipeline)的方式運送封包方式可以達成快速的資料傳送並可減輕在單晶片網路系統擴充上的負擔。

　　我們所提出的路由器可以發展成一個可以讓使用者更換port數目、virtual channel數目、channel寬度、緩衝器大小、不同的路由(包含動態和靜態路由)和仲裁演算法。包含5個port，每個port包含4個32-bit virtual channel的樣板路由器可運作至200MHz，頻寬可到1.6Bbps。這樣的性能已經足夠於映射在NoC上的HDTV的應用。

　　Designing a complex system-on-a-chip (SoC) poses many challenges, such as the integration and reusability of silicon IPs and the scalability of a system. The Networks-on-a-Chip (NoC) is a good solution for these challenges. The adaptive Networks-on-Chip (aNoC) is a template of tiled-architecture consisting of numerous reconfigurable processor cores connected through a structured on-chip interconnection network. Using an interconnection network removes the limit of scalability of bus architecture.

　　However, routing data through an interconnection network can cause the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. This thesis covers the design issues of the on-chip network of the NoC template, and the design and implementation of a router for the on-chip interconnection network of the template. The proposed router adopts a new switching algorithm to accomplish the maximal usage of channels, and the routing module of the router can be easily modularized according to different routing algorithms adopted in the router. The way of transmitting packets by wormhole, virtual channel and pipeline can achieve the fast data transfer and release the overhead of extending the NoC system.

　　The proposed router was developed as an IP of NoC which can be easily modularized for users adopting different number of ports, virtual channels, channel width, buffer size and different routing (including dynamic and static routing) and arbitration algorithms. The benchmark router with 5 ports, each port constants 4 32-bit virtual channels, can operate at 200MHz and the bandwidth can be up to 1.6Gbps. The performance of the router is enough for an HDTV application on NoC.

Abstract Chinese..............................................................i
Abstract English.............................................................ii
Contents....................................................................iii
List of Figures...............................................................v
List of Tables..............................................................vii
Chapter 1 Introduction........................................................1
Chapter 2 Introduction of the aNoC............................................4
1 Why Interconnection Networks............................................4
2 Architectures of the aNoC...............................................6
3 Perspectives of the aNoC................................................8
3.1 Network Perspective of the aNoC.....................................9
3.2 Multiprocessor Perspective of the aNoC.............................10
3.3 Platform Perspective of the aNoC...................................12
Chapter 3 Interconnection Networks...........................................17
1 Classification of Interconnection Networks.............................17
1.1 Shared-medium Networks.............................................18
1.2 Indirect Networks..................................................19
1.3 Direct Networks....................................................24
2 Basic Concepts of Interconnection Networks.............................27
2.1 Layered Protocol Stack Mapping on aNoC.............................27
2.2 Switching Techniques of Interconnection Networks...................30
2.2.1 Circuit Switching..............................................30
2.2.2 Packet Switching...............................................31
        3.2.2.2.1 Stored-and-forward.........................................32
        3.2.2.2.2 Virtual Cut-through........................................33
        3.2.2.2.3 Wormhole...................................................34
2.2.3 Virtual Channel................................................35
2.2.4 Situations of Undeliverable Packets............................36
2.3 Flow Control.......................................................40
2.4 Routing............................................................41
3 Proposed Interconnection Networks of aNoC..............................42
3.1 Design Decision between Shared Medium, Indirect and Direct Networks42
3.2 Network Topology of aNoC...........................................42
3.3 Switching Technique of aNoC........................................43
4 Router of Direct Interconnection Networks..............................43
4.1 Router Model.......................................................43
4.2 Classification and Design Consideration of a Router................45
Chapter 4 Design of an aNoC Router...........................................50
1 Router Overview........................................................50
1.1 Definition of Terminologies and Parameters.........................51
1.2 Flow of a Packet Traversing the Proposed Router....................53
2 Router Design by Control Data Flow Graph...............................55
2.1 CDFG of NoC Router.................................................55
2.2 CDFG of Input Processing...........................................57
2.3 CDFG of IDLE.......................................................59
2.4 CDFG of Routing Flits..............................................60
2.5 CDFG of Virtual Channel Allocation.................................62
2.6 CDFG of Switch Allocation..........................................69
2.7 CDFG of Switch Traverse............................................75
2.8 Flattened CDFG of NoC Router at 2nd Hierarchy......................77
3 Scheduling of the Proposed Router......................................78
3.1 Non-pipelined Scheduling of the Proposed Router....................78
3.2 Pipeline Analysis and Pipelined Scheduling of the Proposed Router..79
3.3 Scheduling of the Proposed Router at 2nd Hierarchy.................81
4 Architecture of the Proposed Router....................................82
Chapter 5 Implementation of an aNoC Router...................................85
1 Benchmark Router.......................................................85
1.1 Dimension-ordered Routing..........................................86
1.2 Round-robin Arbitration............................................88
2 C Functional Model of the NoC Router...................................92
3 Verilog RTL Model of the NoC Router....................................93
4 Verilog RTL Synthesis of the NoC Router................................94
5 Physical Layout of the NoC Router......................................95
6 Performance of the NoC Router..........................................96
Chapter 6 Conclusion.........................................................98
Reference...................................................................100
                                    

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校內：2006-07-29公開
校外：2006-07-29公開

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