簡易檢索 / 詳目顯示

研究生: 黃詳
Huang, Shiang
論文名稱: 多核心動態平行執行架構之系統設計
Design of a Dynamic Parallel Execution Architecture for Multi-Core Systems
指導教授: 周哲民
Jou, Jer-Min
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 中文
論文頁數: 95
中文關鍵詞: 多執行緒多核心動態平行執行
外文關鍵詞: Transactional Memory, Speculation, Thread Level Speculation
相關次數: 點閱:86下載:5
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在多執行緒多核心處理器的系統架構中,如何讓系統能夠有效率的執行是一個主要的目標。而其中最直接有效的方法就是讓所有的處理器隨時都處在工作的狀態中,並且將程式並行的執行,甚至更進一步地事先提前預測執行以達到最高的使用率。然而,多執行緒多核心處理器之間資料的相依及衝突是主要面對的問題。如何精確且有效的偵測並且解決衝突問題,使得系統可以順利的執行,成為一個必要的議題。Transactional Memory (TM) 是為了簡化平行程式資料的同步,透過保證Transaction在執行時必須保持在原子性(Atomic)以及封閉性(Isolation)的特性下運行。在此有兩個主要的機制:Version management以及Conflict Detection。所謂的Version management就是新舊資料的保存方法,多執行緒動態平行執行時,新資料該如何使用以及舊資料該如何保存。而Conflict Management也就是資料之間的衝突偵測,例如RAW、WAW、WAR。
    目前許多Transactional Memory大部分為更改Cache架構,加入R/W Signature來執行衝突偵測。為了降低複雜度以及可擴充性,這邊設計了一個新的架構Dynamic parallel Execution Architecture with Log – DEAL,利用外加的硬體來完成Version Management、Conflict Detection並且支援預測執行。

    Transactional Memory is a promising parallel programming model that addresses the programmability issue of lock-based applications using mechanism that are transparent to developers. For the multi-thread multi-core processor system architecture, making it to work more efficiently is the most important goal. Three methods were used to improve performance. First, keep all of the processors working as long as possible. Second, make the processes or threads to run in parallel. Third, let the threads execute speculativly. Therefore, the design can improve the utility and performance.
    Most of the Transactional Memory changes cache’s architecture and joins R/W signature for conflict detection. In this paper, a new architecture, Dynamic parallel Execution Architecture with Log – DEAL, was designed. To increase scalability and decrease complexity, some additional hardware was used to support version management and conflict detection. In our design, DEAL can support not only transactional memory but also speculation.

    摘要 III Abstruct IV 誌 謝 V 目 錄 VI 圖 目 錄 VIII 表 目 錄 XI 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機與目的 1 1.3 論文架構 2 第二章 背景與相關研究 3 2.1 Transactional Memory (TM)之介紹 3 2.1.1 Version Management 5 2.1.2 Conflict Detection 8 2.1.3 其他Transactional Memory相關架構說明與介紹 11 2.2 Speculation之概念介紹 19 2.2.1 Speculation執行範例介紹與說明 21 第三章 系統架構設計概念說明 23 3.1 Transaction & Speculation之差異 23 3.2 設計概念Transaction for Speculation 24 3.3 Speculative Transaction說明與分析 26 3.4 DEAL系統架構中之運行規則整理 28 第四章 系統架構DEAL設計概念 31 4.1 DEAL系統架構之說明 31 4.1.1 DEAL系統設計之單元介紹 31 4.1.2 DEAL系統架構之執行模式 39 4.2 詳細說明Control Processor架構之設計 40 4.2.1 Control Processor執行過程 40 4.2.2 Control Processor各種中斷請求與處理 42 4.2.3 DEAL’s Control Processor演算法 43 4.3 DEAL範例演練說明 51 4.3.1範例一 Processes同時執行範例 52 4.3.2 範例二 Parallel Processing with conflict 58 第五章 DEAL系統架構實驗數據與範例演練 68 5.1 STAMP: Stanford Transactional Applications for Multi-Processing 模擬與驗證 68 5.2 利用QEMU模擬DEAL架構並驗證設計 76 第六章 結論與未來研究 91 6.1 結論 91 6.2 未來研究 92 參考文獻 93

    [1] Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill & David A. Wood. LogTM: Log-based Transactional Memory. In the proceedings of the 12th Annual International Symposium on High Performance Computer Architecture (HPCA-12) Austin, TX February 11-15, 2006
    [2] Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, David A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In the proceedings of the 13th Annual International Symposium on High Performance Computer Architecture (HPCA-13) Phoenix, AZ February 10-14, 2007
    [3] Jayaram Bobba. Hardware Support For Efficient Transactional and Supervised Memory Systems. Ph.D. Thesis, THE UNIVERSITY OF WISCONSIN - MADISON, 2010
    [4] Marc Lupon, Grigorios Magklis, Antonio González. Version Management Alternatives for Hardware Transactional Memory. In Proceedings of the 9th Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, (MEDEA'08), Toronto (Canada), October 2008.
    [5] Luis Ceze, James Tuck, C˘alin Cas¸caval and Josep Torrellas. Bulk Disambiguation of Speculative Threads in Multiprocessors. In Proc. of the 33nd Annual International Symp. on Computer Architecture, June 2006.
    [6] L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In Procs. of the 31st Intl Symp on Computer Architecture, June 2004.
    [7] Venkata Krishnan and Josep Torrellas. Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip_Multiprocessor. in Proc. of ACM Int. Conf. on Supercomputing, pp. 85-92, 1998.
    [8] Neil Amar Vachharajani. Intelligent Speculation For Pipelined Multithreading. PhD thesis, Department of Computer Science, Princeton University, Princeton, New Jersey, United States, November 2008.
    [9] Garzaran, M. J., M. Prvulovic, et al. (2003). Tradeoffs in buffering memory state for thread-level speculation in multiprocessors. High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on.
    [10] C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford Transactional Applications for Multi-Processing. In Procs. of The IEEE Intl Symp on Workload Characterization, Sept. 2008.
    [11] Minh, C. C., M. Trautmann, et al. (2007). An effective hybrid transactional memory system with strong isolation guarantees. Proceedings of the 34th annual international symposium on Computer architecture. San Diego, California, USA, ACM: 69-80.
    [12] D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In DISC, pages 194–208, 2006.
    [13] Madriles, C., P. L, et al. (2009). Boosting single-thread performance in multi-core systems through fine-grain multi-threading. Proceedings of the 36th annual international symposium on Computer architecture. Austin, TX, USA, ACM: 474-483.
    [14] Lupon, M., G. Magklis, et al. (2010). A Dynamically Adaptable Hardware Transactional Memory. Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on.
    [15] M. Herlihy and J. E. B. Moss, “Transactional Memory : Architectural Support for Lock-Free Data Structures,” in Procs. of the 20th Intl Symp on Computer Architecture, May 1993.
    [16] J. Bobba, N. Goyal, M. D. Hill, M. M. Swift, and D. A. Wood. TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In Procs. of the 35th Intl
    [17] J. Bobba, K. E. Moore, L. Yen, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. Performance Pathologies in Hardware Transactional Memory. In Procs. of the 34th Intl Symp on Computer Architecture, June 2007.
    [18] Madriles, C., P. Lopez, et al. (2009). Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on.
    [19] Di Gregorio, L. (2009). A distributed hardware algorithm for scheduling dependent tasks on multicore architectures. Intelligent solutions in Embedded Systems, 2009 Seventh Workshop on.
    [20] Devietti, J., B. Lucia, et al. (2010). "DMP: Deterministic Shared-Memory Multiprocessing." Micro, IEEE 30(1): 40-49.
    [21] Sohi, G. S. and A. Roth (2001). "Speculative multithreaded processors." Computer 34(4): 66-73.
    [22] Shaogang, W., X. Weixia, et al. (2009). DTM: Decoupled Hardware Transactional Memory to Support Unbounded Transaction and Operating System. Parallel Processing, 2009. ICPP '09. International Conference on.

    下載圖示 校內:2013-08-29公開
    校外:2013-08-29公開
    QR CODE