本晶片利用回授控制機制的方式來實現具頻率輸出之可調整動態範圍的CMOS影像感測器。整體架構包含 的像素陣列、行處理電路、行及列的移位暫存器、偏壓電路、數位緩衝器。而行處理電路中包括比較器、D型閂鎖器、八位元計數器以及記憶體。本架構的特色在於能夠藉由改變比較器中的參考電壓或是每一列像素的讀取時間來調整影像的動態範圍。模擬結果顯示出此影像感測器原先的動態範圍為78dB，在高照度時藉由調整過後可達到100dB，總共改善了22dB。
像素的部份採用類似於傳統3T架構的像素，但額外增加了兩顆電晶體，分別用來改善像素的轉換增益以及提高讀取時的精準度。而晶片的數位控制訊號是經由FPGA產生，除了在測試時具有更大的彈性之外，還可以降低設計電路時的複雜度。
本晶片使用台積電 2P4M 3.3V混合訊號製程，晶片面積 ，像素面積 ，其內部使用N-well/P-sub接面的光二極體，且填充率達38.6%。

This test chip is used feedback mechanism to realize a frequency output CMOS image sensor with adaptive dynamic range. The full chip consists of 64 64 pixel arrays, column processing circuits, column and row shift register, biasing circuit and digital buffer. And column processing circuits comprise comparator, D flip-flop, an eight bits counter and memory. This structure characters the adaptive dynamic range by adjusting the reference voltage of comparator or readout time of one-row pixel. Simulation results show that the dynamic range of the sensor is 78dB originally and achieves to 100dB in high illumination after adjusting parameters. It can extend dynamic range of 22dB.
This sensor adopts 3T-like pixel which has extra two transistors to improve the conversion gain of pixel and achieve higher precision in readout. Furthermore, the digital control signal is generated by FPGA. It not only has larger flexibility in test but also reduce the circuit complexity.
The test chip is fabricated in TSMC 0.35μm 2P4M 3.3V mixed-mode process and occupies the area of 1.684×1.641 mm2. Each pixel adopts N-well/P-sub photodiode and measures the area of and fill-factor of 38.6%.

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