本論文主旨在將具有線上學習的功能之類神經模糊網路設計成一個低功率和高表現的硬體電路。在硬體電路之整體效能評量方面，由於平均功率消耗(P)、延遲(D)和晶片面積消耗(A)彼此之間之互相影響，無法同時達到最小值；因此，為使整體設計達到最佳表現，研究目標為利用有效之設計方法，達到平均功率消耗、計算執行時間和晶片面積消耗的乘積(PDA)之最小值。首先，我們利用了高階合成設計概念對於整體類神經模糊網路做排程和配置，並比較排程和配置後的結果。由此結果推演出新的排程演算法，進而使整體設計晶片面積達到最小值。接著，再藉由實現各種不同管線式(pipeline)架構之類神經模糊網路之電路的波形和合成資訊來比較其優缺點，並應用低功率電路設計理論來降低功率消耗和方法且結合動態控制步驟(dynamic control steps)加快執行速度。從模擬結果我們發現，結合全域性非同步與區域性同步(globally-asynchronous locally-synchronous)之前饋電路與同步(synchronous)管線式之倒傳遞演算法電路可達成本研究目標。最後，將電路實際測試於智慧型駕車系統軟硬體模擬平台上，驗證其效能。

This study focuses on the digital hardware design of an adaptive neuro-fuzzy (NF) network with high performance and low power consumption. In the performance evaluation of a hardware design, since there is a tradeoff among power, delay, and area consumption, it is difficult if not impossible to reach their minima simultaneously. Hence, our design objective is to minimize the cost function, formulated as the product of power, delay (execution time) and area consumption (PDA), of the hardware design of the neuro-fuzzy network. First, based on the concepts of the high level synthesis, we scheduled the data flow graph (DFG) of the NF network and allocated the required functional units of the network computation. According to the scheduling and allocation results, we developed a novel datapath scheduling algorithm which can minimize the area of the NF chip. Next, we accessed the advantages and drawbacks of different pipeline structures by comparing the waveforms and synthesis results of different pipeline structures implemented on NF network. We then applied low-power designs and dynamic control steps to the structures for reducing the power consumption and increasing the execution time, respectively. From the simulations and synthesis results, we found that the structure with minimum PDA is to implement the feedforward and backpropagation circuit of the NF network in a globally-asynchronous locally synchronous (GALS) structure and a synchronous pipeline structure, respectively. Finally, the effectiveness of our design has been validated in the hardware/software co-simulation platform of an intelligent car-driving system.

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