成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	林慶鈞 Lin, Chin-Chun
論文名稱：	適用於調頻廣播之前端接收電路 A CMOS FM Broadcast Receiver Front-End IC
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	79
中文關鍵詞：	互補金氧半導體、調頻、接收機、廣波
外文關鍵詞：	broadcast, CMOS, FM, receiver
相關次數：	點閱：149 下載：2
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

　　本論文描述一個應用於調頻廣播系統，接收頻率在88~108 MHz之間的單一互補金氧半導體接收器晶片。為了實現單一積體化，我們採用了Low-IF的接收機架構以降低類似晶片外映像拒斥濾波器(off-chip image-reject filter)的使用，且在此同時，也可以避免類似直接降頻接收器所導致的直流偏差(DC-offset)和自我混波(self-mixing)問題。此互補金氧半導體調頻廣播接收器前端電路採用quadrature low-IF的架構，主要包含：首先是雙端輸入低雜訊放大器；接著的是Hartley架構的映像拒斥混波電路，其中有 I/Q主動式移頻混波器、二階低通濾波器、相位延遲器；最後是切換電容式的十階帶通濾波器。在這裡，接收的前端電路，可以使得高頻的輸入訊號，降頻至中頻頻率在225 kHz的同相位以及相位差90的中頻訊號。透過映像拒斥混波電路提高在映像拒斥的能力。

　　本接收器電路是採用0.18微米單多晶層六金屬層之混合訊號製程來設計，結果顯示當高頻的輸入訊號操作頻率在88~108 MHz之間，訊號的頻寬為200kHz，最大訊號對雜訊和失真比(PSNDR)為44.3 dB，最大訊號對雜訊比(PSNR)為45.3 dB，動態範圍(dynamic range)為70dB。當工作電壓操作在1.8伏特時，此接收電路的消耗功率為63毫瓦，晶片總面積為0.93mm1mm其中不含Pads之面積為0.57mm0.62mm。

　　This thesis describes a single-chip CMOS receiver for FM Stereo Radio system working in the 88~108-MHz range. Low-power single-cell fully-featured radio receivers, with a minimum of external components are hard to find. For a monolithic implementation, the use of the Low-IF architecture alleviates the necessity of off-chip components, used for image-reject passive filtering. At the same time, DC-offset and self-mixing problems arising from direction-conversion architecture are avoided. This CMOS FM receiver frond-end is a quadrature low-IF receiver consisting of a differential-ended low noise amplifier (LNA) connected to Hartley image-rejection mixer, which comprises Inphase/Quadrature interference mixers, second-order filters, and phase shifter, followed by tenth-order switched-capacitor bandpass filter. The frond-end converts the RF signal to differential I and Q signals, centered at 225-kHz. Degrading of image interference characteristic can be avoided by I/Q IF mixers and phase shift network.
　　The receiver fabricated in a 0.18μm 1P6M mixed-signal CMOS mixed-mode process, achieve peak SNDR of 44.3 dB, peak SNR of 45.3 dB and dynamic range of 70dB with signal frequency of 88~108 MHz and signal bandwidth of 200 kHz. The combination draws 63 mW from a 1.8-V supply. The total chip area including bonding pads is 0.93mm1mm where the active area is 0.57mm0.62mm.

Chapter 1	Introduction                                                1
1	Background ........................................................ 1
2	Motivation ........................................................ 2
3	Organization ...................................................... 3

Chapter 2	System Description and Architectures Design                 4
1  Overview FM Receiver Technology ................................... 4
2.1  Integrated Receiver Circuits ................................. 5
2.2  Integrated Bandpass Filters Circuits ......................... 9
2  Alternative Receiver Architectures ................................ 11
2.1  Homodyne Receiver ............................................ 12
2.2  Super-Heterodyne Receiver .................................... 13
2.3  Low-IF Receiver .............................................. 14
2.4  Image-Reject Receiver ........................................ 16
3  Summary ........................................................... 17

Chapter 3	Design and Implementation of FM Receiver Front-End          19
1	FM Receiver Architecture .......................................... 19                                    
2	Low Noise Amplifier Circuit Design ................................ 21
2.1  High Frequency Noise Model ................................... 22
2.2  Basic CMOS LNA Topology ...................................... 24
2.3  FM-Band CMOS LNA Design ...................................... 26                               
3	Mixer Circuit Design .............................................. 33
3.1  Mixer Topologies ............................................. 33
3.2  FM-Band CMOS Gilbert-Type Mixer Circuit Design ............... 34
4	IF Filtering Circuit Design ....................................... 38 
4.1  Lowpass Filter Circuit Design ................................ 38
4.2  90 Degree Phase Shift Circuit (All-Pass Filter, APF) Design .. 44
4.3  IF Image-Rejection Filters for FM Receiver ................... 45
5	Switched-Capacitor Bandpass Filter Circuit Design ................. 47
5.1  Introduction of Switched-Capacitor Circuits .................. 47
5.2  Characteristics of Inverse Chebyshev Filter .................. 52
5.3  Filter Transfer Function ..................................... 54
5.4  SC BPF Filter Implementation ................................. 60
6	Operational Amplifier Circuit Design .............................. 62
7	Summary ........................................................... 65

Chapter 4     Implementation and Experiment Results                         66
1	Floor Plan and Layout Considerations .............................. 66
2	Simulation Result ................................................. 69
3	Measurement Setup ................................................. 71
4	Summary ........................................................... 73

Chapter 5	Conclusions and Future Work                                 75     							    
Bibliography                                                                77
                                    

[1] Kave Kianush, and Sjakko Sandee, “ Integrated Adaptive Channel Selectivity for FM Receivers,” IEEE International Solid-State Circuits Conference, pp. 388-389, 2000.

[2] Taiwa Okanobu, and Toshiaki Tsuchiya, “ A Complete Single Chip AM/FM Radio Integrated Circuit,” IEEE Trans. Consumer Electron. vol. CE-28, pp. 393–408, Aug. 1982.

[3] Taiwa Okanobu, Hitoshi Tomiyama, and Hiroshi Arimoto, “ Advanced Low Voltage Single Chip Radio IC,” IEEE Trans. Consumer Electron. vol. 38, pp. 465–475, Aug. 1992.

[4] Daisuke Yamazaki, Chikara Nishi, and Taiwa Okanobu, “ A Complete Single Chip AM Stereo/FM Stereo Radio IC,” IEEE Trans. Consumer Electron. vol. 40, pp. 563-569, Aug. 1994.

[5] Taiwa Okanobu, and Hitoshi Tomiyama, “ An Advanced Low Power Radio 1 Chip IC,” IEEE Trans. Consumer Electron. vol. 40, pp. 842-851, Aug. 1994.

[6] Lothar Vogt, Dan Brookshire, Stefan Lottholz, and Guenther Zwiehoff “ A Two-Chip Digital Car Radio,” IEEE International Solid-State Circuits Conference, pp. 350-351, 1996.

[7] Kave Kianush, “ A Complete AM/FM Stereo Receiver and Tuning System on a Single Chip,” IEEE International Solid-State Circuits Conference, pp. 256-257, 1996.

[8] Matthijs Pardoen, John Gerrits, Vincent von Kaenel, “ A 0.9V 1.2mA 200MHz BiCMOS Single-Chip Narrow-Band FM Receiver,” IEEE International Solid-State Circuits Conference, pp. 348-349, 1996.

[9] Taiwa Okanobu, Hitoshi Tomiyama, and Yukinobu Kawamura, “ An AM/TV/FM Stereo Radio IC Including IF Filters for a DTS,” IEEE Trans. Consumer Electron. vol. 43, pp. 655-661, Aug. 1997.

[10] K. Kianush, C. Vaucher, “ A Global Car Radio IC with inaudible Signal Quality Checks,” IEEE International Solid-State Circuits Conference, pp. 130-131, 1998.

[11] Hans Brekelmans, “ A Novel Multistandard TV/FM Front-End for Multimedia Applications,” IEEE Trans. Consumer Electron. vol. 44, pp. 280-288, Aug. 1998.

[12] B-S. Song, and Jeffrey R. Barner, “ A CMOS Double-Heterodyne FM Receiver,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 916-923, Dec. 1986.

[13] B-S. Song, “ A Narrow-Band CMOS FM Receiver Based on Single-Sideband Modulation IF Filtering,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 1147-1154, Dec. 1987.

[14] A. A. Abidi, “ Radio-Frequency Integrated Circuits for Portable Communications,” IEEE Custom Integrated Circuits Conference, pp. 8.1.1-8.1.8, 1994.

[15] “AN192, A Complete FM Radio on a Chip,” Philips Semiconductors, Data Sheet.

[16] “TDA700, FM Radio circuit,” Philips Semiconductors, Data Sheet.

[17] “TDA5768HL, Low-power FM stereo radio for handheld applications,” Philips Semiconductors, Data Sheet.

[18] G. A. De Veirman, and R. G. Yamasaki, “Design of a bipolar 10-MHz programmable continuous-time 0.05° equiripple linear phase filter,” IEEE J. Solid State Circuits, vol. 27, pp. 324-331, Mar. 1992.

[19] T. C. Choi, R. T. Kaneshiro, R. W. Brodersen, P. R. Gray, W. B. Jett, and M. Wilcox, “High-Frequency CMOS Switched-Capacitor Filters for Communications Application,” IEEE J. of Solid-State Circuits, vol. SC-18,
pp. 652-663, Dec. 1983.

[20] P. J. Quinn, K. van Hartingsveldt, and Arthur H. M. van Roermund, “A 10.7-MHz CMOS SC Radio IF Filter Using Orthogonal Hardware Modulation,” IEEE J. of Solid-State Circuits, vol. 35, pp. 1865-1876, Dec. 2000.

[21] A. Nagari, and G. Nicollini, “A 3 V 10 MHz Pseudo-Differential SC Bandpass Filter Using Gain Enhancement Replica Amplifier,” IEEE J. of Solid-State Circuits, vol. 33, pp. 626-630, Apr. 1998.

[22] A. Nagari, A. Baschirotto, F. Montecchi, and R. Castello, “ A 10.7-MHz BiCMOS High-Q Double-Sampled SC Bandpass Filter,” IEEE J. of Solid-State Circuits, vol. 32, pp. 1491-1498, Oct. 1997.

[23] G. Nicollini, F. Moretti, and M.Conti, “ High-frequency fully differential filter using operational amplifiers without common-mode feedback,” IEEE J. of Solid-State Circuits, vol. 24, pp. 808-813, Jun. 1989.

[24] B-S. Song, “ A10.7-MHz Switched-Capacitor Bandpass Filter,” IEEE J. of Solid-State Circuits, vol. 24, pp. 320-324, Apr. 1989.

[25] B-S. Song, and P. R. Gray, “ Switched-Capacitor High-Q Bandpass Filters,” IEEE J. of Solid-State Circuits, vol. SC-21, pp. 924-933, Dec. 1986.

[26] Y. P. Tsividis, “ Integrated continuous-time filter design - an overview,” IEEE J. of Solid-State Circuits, vol. 29, pp. 166-176, Mar. 1994.

[27] J. Silva-Martinez, M. S. J. Steyaert, W. Sansen, “ A10.7-MHz 68-dB SNR CMOS Continuous-Time Filter with On-Chip Automatic Tuning.” IEEE J. of Solid-State Circuits, vol. 27, pp. 1843-1853, Mar. 1992.

[28] Yun-Ti Wang, F. Lu, A. A. Abidi, “ A 12.5MHz Continuous Time Bandpass Filter,” IEEE International Solid-State Circuits Conference, pp. 198-199, 1989.

[29] C.-F. Chiou, R. Schaumann, “Design and performance of a fully integrated bipolar 10.7-MHz analog bandpass filter,” IEEE J. of Solid-State Circuits, vol. SC-21, pp. 6-14, Mar. 1986.

[30] F. Krummenacher, and G. V. Ruymbeke, “ Integrated Selectivity for Narrow-Band FM IF Systems," IEEE J. Solid-State Circuits, pp. 757-760, Jun. 1990.

[31] L-J Pu, and Y. P. Tsividis, “ Transistor-Only Frequency-Selective Circuits," IEEE Journal of Solid-State Circuits, vol. SC-25, pp. 821-832, Jun. 1990.

[32] T. Adachi, A. Ishikawa, K. Tomioka, S. Hara, K. Takasuka, H. Hisajima, A. Barlow, “ A Low Noise Integrated AMPS IF Filter,” IEEE Custom Integrated Circuits Conference, pp. 159-162, 1994.

2005-07-15公開

簡易檢索 / 詳目顯示

相關論文