在本論文提出了一種使用於具掃描架構與邏輯矩陣之測試晶片並針對複數錯誤的新型診斷流程。考慮的錯誤包含向量錯誤、定值錯誤及橋接錯誤。使用本地掃描致能訊號可以完全各別控制掃描鍊。我們可以透過無故障的掃描鍊來傳遞測試向量及邏輯單元塊的響應來避免受到其他錯誤的影響。診斷流程由四個可提升診斷率且減少錯誤候選的數量的測試所組成。分析結果顯示當考慮包含0、1或2個橋接錯誤之雙重錯誤，我們的診斷流程能分別在99.815%、99.753%與99.327%的情況下達到完美的診斷解析度並能分別在99.952%、99.781%與99.341%的情況下達到100%的準確度。另外，在執行完提出的診斷流程後，在分不開的錯誤對中的錯誤都會是功能等同錯誤。

This thesis presents a novel diagnostic procedure for a scan-based test chip architecture targeting the diagnosis of multiple faults. The faults considered include input pattern faults, stuck-at faults, and bridging faults. With local scan enable signals, the scan chains can be fully controlled. We can apply patterns and observe the responses of logic blocks from the fault-free scan chains without being affected by other faults. The diagnostic procedure is composed of four tests that enhance the diagnosability and reduce fault candidates. Evaluation results show that the proposed diagnostic procedure can achieve perfect resolution for 99.815%, 99.753%, and 99.327% of the faults and achieve 100% accuracy for 99.952%, 99.781%, and 99.341% of the faults when double faults containing 0, 1, and 2 bridging faults are considered, respectively. Moreover after applying the proposed diagnostic procedure, the undistinguished fault pairs are all functional equivalent faults.

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