在現今的嵌入式處理器通常會有快取記憶體系統，而在測試這些快取記憶體系統常會使用到自我測試或是可測試電路設計技術。然而，這些在電路中額外增加之測試電路將會影響到快取記憶體本身的效能。因此，有一種無傷害的測試方法叫軟體測試方法來解決快取記憶體的測試問題。此方法使用處理器本身的資源來測試快取記憶體，不需要增加任何的測試電路或修改處理器的設計就可以達到良好的測試效果，所以適用於現今高效能的處理器。在本論文中，我們針對直接映射快取記憶體提出一軟體測試方法，此方法可分為測試記憶體部份與測試控制邏輯部份。在記憶體部份，我們提出一方法來轉換目前較常用的March演算法來達到較高的記憶體測試效果。而在測試控制邏輯部份，我們針對快取記憶體的暫存器傳輸階級描述與較常見的快取記憶體的控制功能來發展測試程式。當然，發展測試程式都是以每一個元件來發展最佳的測試效果。因此，我們所提出的測試方法都可以達到較高的錯誤涵蓋率。
為了驗證我們的測試方法，我們使用一個擁有直接映射記憶體的處理器來當我們的測試樣本。實驗結果顯示我們所提出的軟體測試方法對直接映射記憶體為一極佳之測試解決方案。最後，在我們所提出的測試方法對資料快取的控制邏輯可以達到98%的錯誤涵蓋率。

The cache system is generally implemented in embedded processors. Testing a cache system may use built-in self-test or design-for-test techniques. However, insertion of test circuits would cause performance degradation. Hence, the software-based self testing methodology which uses processor resources to test the cache in the embedded processor is commonly used for high performance consideration. In this thesis, we propose a software-based test methodology for memories and logic modules in the direct-mapped data cache. For the memories, we focus on proposing the transformation methodology to translating March algorithms into executable processor instructions to achieve high test quality. For logic modules, we consider the register transfer level description of components and commonly used cache functions to develop the test sequences. Based on the developed test sequences, high fault coverage for the logic modules can be achieved.
For purpose of illustration, a RISC processor that embeds a direct-mapped data cache is employed for the experiments. The experimental results show that quite high fault coverage can be achieved for both the memories and logic modules by using the proposed test methodology, thereby providing an applicable method that can effectively address the testing issue of direct-mapped data cache. Finally, the Un-collapsed fault coverage can be achieved 98% for the control logic of data cache.

[1] S. Kornauck, L. McNaughton, R. Gibbins, and B. N.Dostie, “A High Speed Embedded Cache Design with Non-intrusive BIST,” in Proc. Int’l Workshop Memory Technology, Design, and Testing, pp. 40-45, 1994.
[2] A. J. van de Goor and Th J. W. Verhallen, “Functional Testing of Current Microprocessor (applied to the Intel i860TM),” in Proc. Int’l Test Conf., pp. 684, 1992.
[3] J. Sosnowski, “In System Testing of Cache Memories,” in Proc. Int’l Test Conf., pp. 384-393, 1995.
[4] S. M. Al-Harbi and S. K. Gupta, “A Methodology for Transforming Memory Tests for In-System Testing of Direct-Mapped Cache Tags,” in Proc. 16th VLSI Test Symp., 1998, pp. 394-400.
[5] C.-C. Wang, “A Dual RISC Core SoC Platform”, M.S. thesis, National Cheng Kung University, 2004.
[6] H.-W. Kao, “Embedded Processor Verification using Particular Characteristics of Linux Operating System”, M.S. thesis, National Cheng Kung University, 2006.
[7] ARM Architecture Reference Manual. Available: http://www.arm.com.
[8] ARM922T Technical Reference Manual. Available: http://www.arm.com.
[9] R. Dekker, F. Beenker, and L.Thijssen, “A Realistic Fault Model and Test Algorithms for Static Random Access Memories,” IEEE Trans. Computer, Vol. 9, No. 6, pp. 567-572, June 1990.
[10] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, Wiley Publisher, 1991.
[11] M.-C. Huang, “Functional Testing for Cache Memory Systems”, M.S. thesis, National Cheng Kung University, 1998.
[12] H.-M. Hsu, “Software-Based Test Methodology for Fully Associative Data Cache”, M.S. thesis, National Cheng Kung University, 2006.
[13] S.R. Makar and R.J. McCluskey, “On the Testing of Multiplexer”, in Proc. Int’l Test Conf., pp. 669-679., 1988
[14] I. Bayraktaroglu, J. Hunt and D. Watkins, “Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues”, Int’l Test Conf., pp. 1-7., 2006.
[15] N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-based self-testing of embedded processors”, IEEE Transactions on Computers, vol.54(4), pp. 461-475, April 2005
[16] Chen and S. Dey, “Software-based self-testing methodology for processor cores,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20(3), pp. 369-380, March 2001.
[17] Cadence Inc, Available: http://www.cadence.com/
[18] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: A Fast Memory Fault Simulator,” in Proc. Int’l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 165-173. , 1999
[19] Synopsys Inc., Available: http://www.synopsys.com/
[20] “TurboScan Reference Manual”, Syntest Corporation, version 2.6, August 2002, Available:http://www.syntest.com/
[21] ARM corporation, Available: http://www.arm.com/