| 研究生: |
葉翼萍 Yeh, Yi-Ping |
|---|---|
| 論文名稱: |
適用於遞迴式修正型離散正餘弦與傅立葉轉換之免係數記憶體-共架構設計 Hardware-Efficient and Coefficient Memory-Free Design with the Common Architecture Implementation of the Recursive MDCT, MDST, IMDCT, IMDST and DFT Algorithms |
| 指導教授: |
雷曉方
Lei, Sheau-Fang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2012 |
| 畢業學年度: | 100 |
| 語文別: | 中文 |
| 論文頁數: | 131 |
| 中文關鍵詞: | 多格式 、共架構設計 、修正型離散正弦轉換 、修正型離散餘弦轉換 、遞迴式傅立葉轉換 |
| 外文關鍵詞: | Multi-Standard, Common Architecture Design, Modified Discrete Sine Transform, Modified Discrete cosine Transform, Recursive Discrete Fourier Transform |
| 相關次數: | 點閱:88 下載:0 |
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隨著多媒體技術的發展,輕薄短小已成為行動裝置的基本訴求,如何將高複雜度的運算以硬體加速化來支援多種規格與功能的多媒體產品,儼然成為一個重要的議題。本論文針對多規格與成本資源上的考量,提出修正型離散正弦正/逆轉換、修正型離散餘弦正/逆轉換和遞迴式傅立葉轉換的共架構設計。運用簡單的前後處理,將五種轉換推導為共架構的形式;並透過演算法本身的對稱性與係數週期性,利用遞迴運算自動產生係數值,用以大量減少多規格所衍生的係數記憶體龐大問題,進而探討硬體的共用性並減少其運算複雜度,達到硬體資源共享。在硬體實現上,可支援MPEG-1 Layer I-III、AAC和E-AC-3的濾波器組與心理聲響模型分析所需的頻譜轉換,整體電路架構僅需2個乘法器和4個加法器,以製程為TSMC 0.18μm 1P6M CMOS的技術下邏輯閘數目約30.3K,操作頻率為52.63MHz,適合應用於支援多格式的音訊行動裝置。
Digital audio coding has become more and more popular and indispensable feature of consumer electronics in recent years. For the portable devices and consumer interest, a multi-standard design on a single device has found widespread use in popular audio applications. In this thesis, we propose a compact common-architecture design for computing the modified discrete cosine transform (MDCT), modified discrete sine transform (MDST), inverse modified discrete cosine transform (IMDCT), inverse modified discrete sine transform (IMDST) and discrete fourier transform (DFT). With a simple preprocessor, the proposed algorithm, which can be derived into a common computation, requires low computational complexity and is applied on MPEG-1 Layer I to III ( 12 / 36 – MDCT / MDST / IMDCT / IMDST, 512 / 1024 – DFT ), AAC ( 256 / 2048 – MDCT / MDST / IMDCT / IMDST, 256 / 2048 - DFT) and E-AC-3 ( 256 / 512 – MDCT / MDST / IMDCT / IMDST ). In the architecture, a high-throughput, coefficient memory-free and hardware-sharing architecture is developed include which can be configured for different transforms. Furthermore, this design is synthesized using TSMC 0.18μm 1P6M CMOS technology and takes about 30.3K gates while the max clock rate is 52.63MHz.
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校內:2017-08-30公開