簡易檢索 / 詳目顯示

回結果列表
研究生： 廖凡緯
Liao, Fan-Wei
論文名稱： 具背景校正技術十四位元每秒八億次四倍分時導管式類比數位轉換器
A 14-bit 800MS/s 4-way Time-Interleaved Pipelined ADC with Digital Background Calibration
指導教授： 郭泰豪
Kuo, Tai-Haur
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 92
中文關鍵詞： 導管式類比數位轉換器 、數位背景式校正 、分時多工
外文關鍵詞： pipelined ADC, digital background calibration, time-interleaved
相關次數： 點閱：141  下載：17 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 導管式類比數位轉換器因架構特性常被用於實現高速高解析之規格，但為達高解析度必須克服放大器造成的誤差，包括有限增益誤差、放大器偏移誤差以及失真誤差。本論文提出創新Dual-residue Split-ADC架構及其數位背景式校正技術用以校正放大器誤差，如此可採用低成本低功耗之放大器，且此技術同時具有低複雜度與高收斂速度的特性。此外，本校正技術亦可應用於分時多工導管式類比數位轉換器，相比於傳統分時多工架構不需額外校正通道誤差中的增益誤差與偏移誤差，而通道的時間飄移誤差則可藉由本論文另外提出的具同步取樣機制之自舉電路克服。
    本論文所提出的創新Dual-residue Split-ADC架構及其數位背景式校正技術以TSMC 40nm 1P9M CMOS製程實現於十四位元每秒八億次取樣之四倍分時多工導管式類比數位轉換器，並使用多位元前級搭配開回路架構進而降低整體功耗。由Post-sim模擬結果顯示，當輸入訊號為370MHz且取樣頻率為800MS/s，校正前SNDR為37.3 dB，而校正後SNDR可上升至66.8 dB。在電源電壓為1V時且不含輸出緩衝器下，整體ADC的功耗僅83.8mW，ADC效能指標FOM可達到58.5 fJ/conversion.step。

    Pipelined ADCs are usually implemented for high-speed high-resolution applications. However, to achieve high resolution, the error induced by the opamp must be eliminated, including finite opamp gain error, opamp offset and distortion error. This thesis proposes a dual-residue split-ADC architecture and digital background calibration technique for opamp errors, so that a low-cost low-power amplifier could be used. This architecture and calibration technique have the benefits of low complexity and high convergence. Moreover, these techniques can be used in time-interleaved pipelined ADCs. Compared with the traditional TI-ADC, the additional cost for calibrating channel mismatches, which includes gain error mismatch and offset mismatch, is unnecessary. Besides, the timing mismatch could be overcome by a bootstrapped switch, which is embedded in the global sampling techniques proposed in this thesis.
    The proposed dual-residue split-ADC and calibration technique are implemented in a 14-bit 800MS/s four-way time-interleaved pipelined ADC fabricated in TSMC 40nm 1P9M CMOS process. A multi-bit front-end stage and open-loop architecture are implemented in this work for power saving. The post-simulation results show that the SNDR before calibration is 37.3 dB and improved after calibration to 66.8 dB at 370MHz input frequency and 800MS/s sampling rate. The power consumption is 83.8mW from a 1V supply excluding output buffer. The Figure of Merit (FOM) of this prototype ADC is 58.5 fJ/conversion.step.

    Chapter1 Introduction 1 1.1 Motivation 1 1.2 Organization 3 Chapter2 Error Analyses of TI-Pipelined ADC 4 2.1 Quantization error 4 2.2 Clock Jitter 5 2.3 Noise 6 2.4 Comparator offset in sub-ADC 11 2.4.1 The effect of comparator offset in sub-ADC 14 2.4.2 Digital error correction (DEC) 14 2.5 Sampling Mismatch between Sub-ADC and MDAC 15 2.6 Error in MDAC 16 2.6.1 Error in opamp 17 2.6.2 Capacitor mismatch 19 2.6.3 Reference mismatch in sub-DAC 20 2.7 Channel Mismatch Analyses of TI-ADC 22 2.7.1 Offset error mismatch 23 2.7.2 Gain error mismatch 23 2.7.3 Timing skew mismatch 24 Chapter3 Propose Digital Background Calibration Technique with Split-ADC Architecture 26 3.1 Introduction of Split-ADC Architecture 28 3.2 Characteristic in proposed calibration technique 29 3.3 Error detection and correction of proposed calibration 31 3.3.1 Common offset error VOS,CM 32 3.3.2 Common linear gain error εCM 33 3.3.3 Differential offset error VOS,DIF 35 3.3.4 Differential linear gain error εg,dif 39 3.3.5 Distortion error k3 41 3.4 Over-range issue with proposed calibration techniques 43 3.5 Calibration circuit implementation 45 Chapter4 Circuit Design of 4x Time-Interleaved Pipelined ADC 46 4.1 The Architecture of Proposed ADC 46 4.2 Design consideration of proposed ADC 47 4.2.1 Multi-bit front-end 47 4.2.2 Timing allocation 48 4.2.3 Sampling capacitor requirement 49 4.3 Time-interleaved sample-and-hold (S/H) circuit 50 4.3.1 Critical techniques review 50 4.3.2 Proposed bootstrap circuit embedded global sampling techniques with reliability guarantee circuit 54 4.3.3 Input-feedthrough prevention 55 4.4 Sub-ADC in 1st-stage 55 4.5 Gain stage in 1st-stage (chopping circuit and open-loop amplifier with CMFB) 56 4.5.1 Chopping circuit 57 4.5.2 Open-loop amplifier with CMFB 58 4.5.3 Charge sharing effect of open-loop system 59 4.6 Digital encoder in 1st-stage 60 4.7 DAC control switch 61 4.8 Design of backend stages 63 4.8.1 Comparator design in 1.5-bit sub-ADC 63 4.8.2 Pseudo-differential MDAC 63 4.8.3 Ring-amplifier 64 4.8.4 Two-bit Flash ADC in last stage 66 4.9 Reference Ladder Consideration 67 4.9.1 Accuracy of reference ladder 67 4.9.2 Inter-channel interference of reference voltage 68 4.9.3 Reference bouncing reduction 70 4.10 Timing Generator Circuit 71 4.10.1 LVDS receiver 72 4.10.2 Multi-phase Clock generator 72 4.10.3 Phase allocation circuit 73 Chapter5 Layout and Measurement Results 75 5.1 Floor Plan and Layout 75 5.2 Simulation result 77 5.3 Measurement Setup 80 5.4 PCB Design Consideration 81 5.4.1 Transmission line effect 81 5.4.2 Parasitic 81 5.4.3 PCB fabrication 83 5.5 Measurement result 85 Chapter6 Conclusion and Future Work 89 Reference 90

    [1] Hegong Wei, Peng Zhang, Bibhu Datta Sahoo and Behzad Razavi, “An 8 Bit 4 GS/s 120 mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1751- 1761, Dec 2014.
    [2] Nicolas Le Dortz, Jean-Pierre Blanc, Thierry Simon and Sarah Verhaeren et al, “A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS,” in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 386 – 388.
    [3] William C. Black, David A. Hodges, “Time interleaved converter arrays,” IEEE J. Solid-State Circuits, vol. 15, no. 6, pp. 1022 - 1029, Dec 1980.
    [4] Mikael Gustavsson and Nianxiong Nick Tan, “A Global Passive Sampling Technique for High-Speed Switched-Capacitor Time-Interleaved ADCs,” IEEE Trans. Circuits Sys. II, vol. 47, no. 9, pp. 821–831, Sept. 2000.
    [5] Dimitris P. Triantis, Alexios N. Birbas and D. Kondis, “Thermal noise modeling for short-channel MOSFETs,” IEEE Transactions on Electron Devices, vol. 43, Issue. 11, pp. 1950 - 1955, Nov. 1996.
    [6] Renuka P. Jindal, “Compact Noise Models for MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, Issue. 9, pp. 2051 - 2061, Sept. 2006.
    [7] Marcel J. M. Pelgrom, Aad C. J. Duinmaijer and Anton P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433 - 1439, Oct. 1989.
    [8] Patrick G. Drennan and Colin C. McAndrew, “Understanding MOSFET Mismatch for Analog Design,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450 - 456, Mar 2003.
    [9] Stephen H. Lewis, H. Scott Fetterman, George F. Gross, R. Ramachandran, T. R. Viswanathan “A 10 b 20 Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351 - 358, Mar 1992.
    [10] Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan et al. “SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1893 - 1903, Aug. 2011.
    [12] Benjamin Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon, “Ring amplifiers for switched capacitor circuits,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2928–2942, Dec. 2012.
    [13] B. Robert Gregoire and Un-Ku Moon, “An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2620–2630, Dec. 2008.
    [14] Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan and Klaas Bult, ”An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2834 - 2844, Dec. 2011 .
    [15] Sedigheh Hashemi and Behzad Razavi, “A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1739 - 1750 , Aug. 2014.
    [16] Ashutosh Verma and Behzad Razavi, “A 10 Bit 500 MS/s 55 mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039 – 3050, Nov. 2009.
    [17] Shafiq M. Jamal, Daihong Fu, Nick C.-J. Chang, Paul J. Hurst and Stephen H. Lewis, “A 10b 120 Msample/s time-interleaved analog-to-digital converter with digital background calibration,” IEEE J. Solid-State Circuits, vol. 37, pp. 1618-1627, Dec. 2002.
    [18] Jipeng Li and Un-Ku Moon, “Background calibration techniques for multistage pipelined ADC’s with digital redundancy,” IEEE Trans. Circuits Sys. II, vol. 50, pp. 531–538, Sept. 2003.
    [19] John McNeill, Michael C. W. Coln, and Brian J. Larivee, “Split ADC’ architecture for deterministic digital background calibration of a 16 bit 1 MS/s ADC,” IEEE J. Solid-State Circuits, vol.40, no. 12, pp. 2437–2445, Dec. 2005.
    [20] Imran Ahmed and David A. Johns, “An 11 bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1626–1637, Jul. 2008.
    [21] Sedigheh Hashemi and Behzad Razavi, ” A 10 bit 1 GS/s CMOS ADC with FOM = 70 fJ/conversion,” in Proc. IEEE CICC, 2012, pp. 1 – 4.
    [22] Peter Bogner, ” A 28 mW 10b 80 MS/s pipelined ADC in 0.13 μm CMOS,”, in Proc. ISCAS, 2004, pp. 17–20.
    [23] Andrew M. Abo and Paul R. Gray, “A 1.5 V, 10 bit, 14.3 MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599 - 606, May 1999.
    [24] Bernhard Wicht, Thomas Nirschl and Doris Schmitt-Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004.
    [25] Jipeng Li and Un-Ku Moon, “A 1.8 V 67 mW 10 bit 100 MS/s pipelined ADC using time-shifted CDS technique,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1468–1476, Sep. 2004.
    [26] Benjamin Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita and Un-Ku Moon, “Ring Amplifiers for Switched Capacitor Circuits,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2942-2928, Dec 2012.
    [27] Xiang Gao, Eric A. M. Klumperink and Bram Nauta, “Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation”, IEEE Trans. Circuits Sys. II, vol. 55, pp. 244–248, March 2008.
    [28] Ahmed M. A. Ali, Huseyin Dinc, Paritosh Bhoraskar, Chris Dillon, Scott Puckett, Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Brad Jeffries, Ushma Mehta, Matthew McShea and Russell Stop, “A 14b 1 GS/s RF sampling pipelined ADC with background calibration,” in IEEE ISSCC Dig. Tech. Papers, 2014, pp. 482–484.
    [29] Andrea Panigada and Ian Galton, “A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 162–164.
    [30] Hans Van de Vel, Berry A. J. Buter, Hendrik van der Ploeg, Maarten Vertregt, Govert J. G. M. Geelen and Edward J. F. Paulus, “A 1.2 V 250 mW 14b 100 MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1047–1056, April. 2009.
    [31] Byung-Geun Lee, Byung-Moo Min, Gabriele Manganaro and Jonathan W. Valvano, “A 14b 100 MS/s Pipelined ADC with a Merged Active S/H and First MDAC,” in Proc. IEEE Int. Solid-State Circuits Conf., 2008, pp. 248–250.
    [32] Peter Bogner, Franz Kuttner, Claus Kropf, Thomas Hartig, Markus Burian and Hermann Eul, “A 14b 100 MS/s digitally self-calibrated pipelined ADC in 0.13 CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 832–841.
    [33] Zwei-mei Lee, Cheng-yeh Wang and Jieh-tsorng Wu, “A CMOS 15 Bit 125 MS/s Time-Interleaved ADC with Digital Background Calibration,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2149 - 2160, Oct. 2007.
    [34] Siddharth Devarajanm, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath and Paul Wilkins, “A 16b 125 MS/s 385 mW 78.7 dB SNR CMOS pipeline ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3305 - 3313, Dec. 2009.
    [35] Michael Anthony, Edward Kohler, Jeffrey Kurtze, Lawrence Kushner and Gerhard Sollner, “A Process-Scalable Low-Power Charge-Domain 13 bit Pipeline ADC,” in Symp. VLSI Circuits Dig., 2008, pp. 222–223.
    [36] Hyun H. Boo, Duane S. Boning and Hae-Seung Lee, “A 12b 250 MS/s Pipelined ADC with Virtual Ground Reference Buffer,” in IEEE ISSCC Dig. Tech. Papers, 2015, pp. 282–284.

    下載圖示 校內：2019-07-27公開
    校外：2019-07-27公開
    QR CODE