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研究生： 蘇巴坦
Tenzing Sherpa
論文名稱： 具有記憶體請求排程機制之SDRAM控制器硬體合成器
A SDRAM Controller with Request Scheduling Hardware Synthesizer
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 69
外文關鍵詞： SDRAM Controller, Request Scheduler, Scheduling Policies, DDR, SDRAM, SDRAM Memory Controller
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    • Memory Controller is a digital circuit responsible for generating the command signals to manage the data transfer to and from Double Data Rate (DDR) SDRAM memory. A DDR SDRAM memory controller could be an independent chip or can be integrated with another chip. The DDR SDRAM Controller is a unit that operates between the SDRAM and the bus master. As the accomplishment margin between processor and memory has been developing essentially, controller design holds a great importance as it should be able to manage the off-chip latency efficiency at its best.
    The controller design for DDR SDRAM requires proper knowledge of the working of a particular DDR generation. This is the reason why most of the available DRAM simulators implement a rather simplistic model of the controller which fails acknowledge the complex behavior of the modern DRAM system altogether.
    Therefore, we propose a SDRAM controller with modular request scheduling hardware synthesizer. It is specifically designed to model and synthesize various configurations of DDR2 and DDR3 as per the specification provided by Micron. Furthermore, we have included a modular request scheduler which includes four scheduling policies to enhance the efficiency and can add more scheduling policies without the need to alter the other units of the controller. The inclusion of a modular request scheduler allows the user to design a controller as per the nature of the expected memory request sequence from one or more sources.

    ACKNOWLEDGEMENT I ABSTRACT II CONTENTS III LIST OF TABLES V LIST OF FIGURES VI CHAPTER 1: INTRODUCTION 1 1.1 OVERVIEW 1 1.2 MOTIVATION 6 1.3 CONTRIBUTIONS 7 1.4 THESIS ORGANIZATION 8 CHAPTER 2: BACKGROUND 9 2.1 DRAM ORGANIZATION 9 2.2 BASICS OF DRAM OPERATION 11 2.3 SDRAM MODE REGISTERS 14 2.4 SDRAM LATENCIES 23 2.5 SCHEDULING POLICIES 25 CHAPTER 3: RELATED WORKS 31 3.1 DRAMSIM2[1] 31 3.2 RAMULATOR[10] 33 3.3 MCSIM[11] 36 3.4 SUMMARY OF RELATED WORKS 39 CHAPTER 4: SDRAM CONTROLLER WITH REQUEST SCHEDULING 41 4.1 MEMORY CONTROLLER ARCHITECTURE 41 4.2 COMMAND GENERATOR FSM STATE DIAGRAM 45 4.3 SDRAM CONTROLLER SYNTHESIZER SETUP 49 CHAPTER 5: RESULTS AND DISCUSSION 52 5.1 SIMULATION SETUP 52 5.2 POST SIMULATION CLOCK PERIOD BOUNDARIES 52 5.3 LATENCY PENALTY FOR SDRAM CONTROLLER SYNTHESIZER 53 5.4 HARDCODED VS COMPATIBLE SDRAM CONTROLLER 55 5.5 POST-SYNTHESIS POWER CONSUMPTION AND AREA REPORT 56 5.6 EXPERIMENT WITH SCHEDULING POLICIES 63 CHAPTER 6: CONCLUSION AND FUTURE WORKS 66 6.1 CONCLUSION 66 6.2 FUTURE WORKS 67 REFERENCE 68

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