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研究生： 陳敬中
Chen, Jing-Zhong
論文名稱： 一個單通道十二位元八千萬赫茲頻寬管線式雜訊整形連續漸進式類比數位轉換器
A Single-channel 74 dB-SNDR 80 MHz BW Pipelined Noise-Shaping SAR ADC
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2026
畢業學年度： 114
語文別： 英文
論文頁數： 163
中文關鍵詞： 管線式類比數位轉換器 、三角積分調變器 、連續漸進式類比數位轉換器 、雜訊整形 、管線式雜訊整形之連續漸進式類比數位轉換器
外文關鍵詞： Pipelined ADC, Delta-Sigma Modulator (DSM), Successive Approximation Register (SAR) ADC, Noise shaping (NS), Pipelined Noise-Shaping SAR (Pi-NS-SAR) ADC
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    • 管線式雜訊整形連續漸進式類比數位轉換器同時結合了三角積分調變器和連續漸進式類比數位轉換器的優點，並透過管線式架構在速度、解析度與功耗表現上取得優勢。
    本論文提出一個利用兩個動態放大器同時實現管線級殘值放大與雜訊整形功能的類比數位轉換器，此架構確保了系統對放大器非理想效應的低敏感度。此外，第一級採用部分迴圈展開技術、非二進制電容權重及背景式補偏校正，使系統在高速操作下仍保有穩定性，且無須耗費大量功耗或面積。
    本設計以台積電 28 奈米 CMOS 製程進行晶片下線驗證。此晶片核心的電路面積為0.022 mm2。在1 V供應電壓、取樣頻率為320 MS/s 下，功耗為2.52 mW。針對 2 MHz (-0.3 dBFs) 輸入訊號，量測結果顯示 SNDR 為 70.1 dB，SFDR 為 87.9 dB， 並且DR為71.2 dB，實現了 172.1 dB 的FoMs 效能指標。為了證明所提出的類比數位轉換器架構對 PVT變化的穩健性，以不同供應電壓(±10%)和溫度(-40~100ºC) 對4顆晶片進行了性能測試，結果為約2 dB的SNDR差異。

    The Pipelined Noise-Shaping SAR (Pi-NS-SAR) ADCs combine the features of Delta-Sigma Modulators (DSM) and SAR ADCs, meanwhile, utilizing pipelined operation to achieve superior speed, resolution, and power efficiency.
    This thesis presents an ADC that realizes both residue amplification and the noise transfer function (NTF) simultaneously through two dynamic amplifiers. This approach ensures the system remains insensitive to the non-ideal effects of the amplifiers. Furthermore, the first stage incorporates partial loop-unrolling, non-binary CDAC weighting, and background offset calibration to guarantee stability during high-speed operation without significant power or area overhead.
    The prototype chip was fabricated in TSMC 28-nm technology with an active area of 0.022 mm2. Operating at a 320 MS/s sampling rate with a 1 V supply, the ADC consumes 2.52 mW. For a 2 MHz (-0.3 dBFs) input signal, the measured SNDR is 70.1 dB, the SFDR is 87.9 dB, and the dynamic range (DR) is 71.2 dB, achieving a Schrier Figure of Merit (FoMS) of 172.1 dB. To validate PVT robustness of the proposed ADC structure, four chips were tested across varying supply voltage (±10%) and temperature (-40~100ºC), showing an SNDR variation of only 2 dB.

    摘 要 I Abstract II Table of Contents V List of Tables X List of Figures XI Chapter 1 Introduction 1 1.1 ADC Figure of Merits and Trends 1 1.2 Organization of the Thesis 3 Chapter 2 Fundamentals of Analog-to-Digital Converter 4 2.1 Introduction 4 2.1.1 Quantization Error 5 2.1.2 Static Specifications 7 2.1.2.1 Offset Error 7 2.1.2.2 Gain Error 8 2.1.2.3 Nonlinearity Error 9 2.1.2.3.1 Differential Non-Linearity (DNL) 9 2.1.2.3.2 Integral Non-Linearity (INL) 10 2.1.3 Dynamic Specifications 11 2.1.3.1 Signal-to-Quantization Noise Ratio (SQNR) 11 2.1.3.2 Signal-to-Noise Ratio (SNR) 12 2.1.3.3 Total Harmonic Distortion (THD) 12 2.1.3.4 Signal-to-Noise and Distortion Ratio (SNDR) 13 2.1.3.5 Effective Number of Bits (ENOB) 14 2.1.3.6 Dynamic Range (DR) 14 2.1.3.7 Spurious-Free Dynamic Range (SFDR) 14 2.1.3.8 Effective Resolution Bandwidth (ERBW) 15 2.2 Nyquist-rate ADC 16 2.2.1 Sampling Theorem 16 2.2.2 Quantizer Topologies 18 2.2.2.1 Flash ADC 18 2.2.2.2 Pipeline ADC 20 2.2.2.3 SAR ADC 22 2.2.3 SAR ADC Building Blocks and Non-ideality Analysis 24 2.2.3.1 S/H 24 2.2.3.1.1 Clock Feedthrough 27 2.2.3.1.2 Charge Injection 27 2.2.3.2 Comparator 29 2.2.3.2.1 Comparator Speed 31 2.2.3.2.2 Comparator Noise 33 2.2.3.2.3 Comparator Offset 33 2.2.3.2.4 Kickback Noise 34 2.2.3.3 CDAC 35 2.2.3.3.1 Thermal Noise 35 2.2.3.3.2 CDAC Mismatch 36 2.2.3.4 Digital Logic 36 2.3 Oversampling ADC 38 2.3.1 Oversampling 38 2.3.2 Noise-shaping 40 2.3.3 Loop Filter Topologies 42 2.3.3.1 Feedback Topology 42 2.3.3.2 Feedforward Topology 44 2.3.4 MASH Structure 46 2.3.4.1 Conventional MASH Structure 46 2.3.4.2 Sturdy-MASH Structure 47 2.3.5 Nosie-coupled Architecture 48 2.3.6 Discrete-time and Continuous-time DSM 49 2.3.6.1 Discrete-time DSM 49 2.3.6.2 Continuous-time DSM 50 2.3.6.3 Comparison of DT-DSM and CT-DSM 52 Chapter 3 Fundamentals of Noise-Shaping SAR ADC and Pipelined-SAR ADC 53 3.1 Hybrid ADC Research Trends 53 3.2 Noise-shaping SAR ADC 54 3.2.1 Loop Filter Improve Technique 55 3.2.1.1 Loop Filter Architecture 55 3.2.1.1.1 CIFF Architecture 56 3.2.1.1.2 EF Architecture 57 3.2.1.2 Signal Summation 58 3.2.1.2.1 Multi-input Comparator 58 3.2.1.2.2 Charge Sharing 59 3.2.1.2.3 Capacitor Stacking 59 3.2.1.3 Loop Filter Gain Stage Design 60 3.2.1.3.1 Closed-loop Amplifier 60 3.2.1.3.2 Fully Passive 61 3.2.1.3.3 Open-loop Amplifier 61 3.2.1.4 Noise-shaping Order Extension 62 3.2.2 CDAC linearity Enhance Technique 63 3.2.2.1 Dynamic Element Matching 63 3.2.2.2 Mismatch Error Shaping 64 3.2.2.3 Foreground Calibration 66 3.2.3 Input Driving and Noise Reduction Technique 67 3.2.4 Time Interleaved Technique 67 3.3 Pipelined-SAR ADC 70 3.3.1 OPAMP Sharing Technique 70 3.3.2 Dynamic Amplifier Technique 71 3.3.2.1 Zero-Crossing-Based Circuits (ZCBC) 72 3.3.2.2 Ring Amplifier 73 3.3.2.3 Floating Inverter Amplifier 75 3.3.4 Auxiliary Technique 77 3.4 Pipelined Noise Shaping SAR ADC 78 Chapter 4 A Single-channel 74 dB-SNDR 80 MHz-BW Pipelined Noise-Shaping SAR ADC 79 4.1 introduction 79 4.1.1 Design Target 79 4.1.2 Potential Architectures 80 4.1.3 State-of-the-Art Design 83 4.1.3.1 TI-NS-SAR ADC 83 4.1.3.2 Pi-NS-SAR ADC 84 4.1.4 Reference Work Analysis 85 4.2 Proposed Architecture 87 4.3 System Level Design 93 4.3.1 Speed Considerations 93 4.3.2 Resolution Considerations 95 4.3.3 Robustness Considerations 97 4.3.3.1 First Stage 97 4.3.3.2 EF Filter 98 4.3.3.3 Residue Amplifier 100 4.4 Circuit Level Design 103 4.4.1 Switch 103 4.4.2 Comparator 105 4.4.3 Digital Control Logic 107 4.4.4 Residue Amplifier 108 4.4.5 CDAC Array 110 4.4.6 LVDS 112 Chapter 5 Simulation and Measurement Results 113 5.1 Layout Floor Plan 113 5.2 Simulation Results 116 5.2.1 Behavioral Model Simulation Results 116 5.2.2 Pre-layout Simulation Results 118 5.2.3 Post-layout Simulation Results 120 5.3 Chip Micrograph and Measurement Setup 124 5.4 Measurement Results 127 5.5 Problem & discussion 131 5.5.1 Output Buffer 131 5.5.2 Interstage Gain Error 133 Chapter 6 Conclusion and Future Works 134 6.1 Conclusion 134 6.2 Future Works 135 Bibliography 136

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