簡易檢索 / 詳目顯示

回結果列表
研究生： 李彥龍
Lee, Yen-Long
論文名稱： 時脈與資料回復電路之設計與抖動容忍度的快速估計技術
Design for Clock and Data Recovery Circuits and Quick Estimation for Jitter Tolerance
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 109
中文關鍵詞： 抖動容忍度測試 、時脈與資料回復電路 、寬範圍頻率偵測器
外文關鍵詞： Clock and data recovery, jitter tolerance test, wide-range frequency detector
相關次數： 點閱：139  下載：32 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 由於乙太網路和晶片間傳輸介面的廣泛運用使得串列與解串列積體電路需求快速增加。在充滿雜訊的環境傳輸資料使得訊號品質不佳，因此在接收端中普遍使用時脈與資料回復電路以確保能正確的回復資料。並且，時脈與資料回復電路必須從接收到的資料萃取出時脈訊號並且重新對資料取樣來移除抖動效應。為了能接收並正確回復具有抖動的資料，電路的抖動容忍度是重要的效能指標之一，但驗證抖動容忍度極其耗時而且高成本。
    我們在本論文中針對時脈與資料回復電路提出三個有效提升效能與降低成本的電路技巧，如下所述：(1)提出一個動態階梯式bang-bang相位偵測器使其具有類線性的轉換特性但仍是以bang-bang的類型操作。利用此相位偵測器不僅可以擴大收斂範圍而且提升抑制抖動的能力；(2)藉由結合數位型正交相關頻率偵測器與次諧波頻率偵測器，提出一個無邊界的頻率偵測機制。可應用於寬範圍頻率的時脈與資料回復電路中，並自動的達成頻率檢測，但此頻率偵測機制僅受限於資料轉態密度；(3)採用主動型電感負載於閘控制壓控震盪器來減少功率消耗與晶片面積，並且在鎖頻模式與資料回復模式中共用兩個半速率閘控制壓控震盪器，使得設計串接型時脈與資料回復電路時可以減少使用一個壓控震盪器。
    除了電路設計之外，另一個是關於快速抖動容忍度估計的測試方法。藉由反轉回復的時脈訊號產生一個0.5 UI的相位移動並獲得追蹤相位的時間來計算出時脈與資料回復電路追蹤相位的能力，再根據獲得的追蹤相位能力去快速的估計抖動容忍度，可以改善耗時的驗證過程並避免使用昂貴的測試機台。

    Demands for Serializer and De-serializer (SerDes) integrated circuits (ICs) have increased due to the widespread use of Ethernet networks and chip-to-chip interfaces. To ensure the input data stream is well recovered in a receiver end, the clock and data recovery (CDR) circuits are widely used. In a noisy transmission environment which causes poor signal integrity, the CDR circuits have to extract the clock information from input data and resample the input data to remove jitter. To characterize the capability of tolerating jitter, the jitter tolerance performance is a critical indicator but the verification task is time-consuming and costly.
    This dissertation presents three improved circuit techniques for CDRs as follows. (1) The proposed dynamic stepwise bang-bang phase detector is a linear-like transfer characteristics but bang-bang operation. It not only enlarges the pull-in range but also enhances the jitter performance. (2) The proposed unbounded frequency-detection mechanism combines the digital quadricorrelator frequency detector (DQFD) and sub-harmonic tone frequency detector (FD) in wide-range CDRs, which achieve automatically frequency detection. The unbounded detection mechanism is limited by the data transition density. (3) The proposed gated voltage-controlled oscillator (GVCO) with active inductive loading technique instead of the on-chip inductor reduces the power consumption and area. Moreover, the two half-rate GVCOs are shared between frequency presetting and data recovery modes to remove one superfluous VCO in designing a cascaded CDR.
    In addition to presenting circuit techniques, a quick jitter tolerance estimation methodology is proposed in this dissertation. The tracking capability of the CDR is obtained by simply inverting the recovered clock to produce a 0.5 unit interval (UI) phase shift and capture the tracking time. Based on the obtained tracking capability, a quick jitter tolerance estimation technique is proposed to simplify the time-consuming process as well as avoid the costly test equipment.

    摘 要 iii Abstract v List of Tables x List of Figures xi Chapter 1 Introduction 1 1.1 Introduction and Motivation 1 1.2 Organization of Dissertation 2 Chapter 2 Background Knowledge of CDR Circuits 4 2.1 Data Signaling Method 4 2.2 CDR Architectures 5 2.2.1 Sub-rate CDR Circuits 6 2.2.2 CDR Circuits with an External Reference Clock 7 2.2.3 Reference-less CDR Circuits 9 2.2.4 Continuous-rate CDR Circuits 9 2.3 Phase Detectors 10 2.3.1 Linear Phase Detector 11 2.3.2 Bang-bang Phase Detector 13 2.4 Frequency Detectors 14 2.4.1 Rotational Frequency Detector 14 2.4.2 Sub-harmonic Tone Frequency Detector 19 2.5 Voltage-controlled Oscillators 21 2.5.1 Delay Interpolating VCO 21 2.5.2 Voltage-controlled Oscillator with Active Inductive Loads 22 2.6 Performance Metrics of Clock and Data Recovery 24 2.6.1 Phase Noise 24 2.6.2 Jitter 25 2.6.3 Jitter Generation 27 2.6.4 Jitter Transfer 27 2.6.5 Jitter Tolerance 28 Chapter 3 Reference-less CDR Using Dynamic Stepwise Bang-bang Phase Detector 30 3.1 Circuit Implementation 31 3.1.1 The Proposed 1/4-rate DQFD & PD 32 3.1.2 The Phase Interpolator 36 3.1.3 The Proposed Dynamic Stepwise Bang-bang PD 37 3.2 Experimental Results 38 Chapter 4 Continuous-rate CDR Using Wide-range Frequency Detector 42 4.1 Bidirectional Frequency Detector 42 4.2 Circuit Implementation 43 4.2.1 Half-rate DQFD & Simplified PD Path 45 4.2.2 Sub-harmonic Tone Frequency Detection Path 48 4.2.3 Band Selection 51 4.2.4 The Effect of Transition Probability 52 4.2.5 Wide Range Voltage-controlled Oscillator 53 4.3 Experimental Results 55 Chapter 5 Cascaded CDR with Active Inductor based VCO 61 5.1 Cascaded CDRs 61 5.2 Circuit Implementation 63 5.2.1 GVCO Architecture 66 5.2.2 GVCO with N-Type Active Inductive Load 68 5.2.3 Phase Frequency Detector and Charge Pump 70 5.2.4 Lock Detector 70 5.3 Experimental Results 71 Chapter 6 Jitter Tolerance Estimation for Bang-bang CDRs 74 6.1 Jitter Tolerance Analysis in Bang-bang CDRs 75 6.2 On-chip Jitter Tolerance Testing 78 6.3 Tracking Capability Testing 80 6.3.1 The Concept of Tracking Capability Testing 80 6.3.2 Tracking Capability Testing for digital bang-bang CDRs 81 6.3.3 Tracking Capability Testing for analog bang-bang CDRs 84 6.4 Jitter Tolerance Estimation 85 6.4.1 Review of Jitter and Jitter Tolerance 85 6.4.2 Jitter Tolerance Estimation Technique 86 6.4.3 Peak-to-peak Jitter Estimation 89 6.4.4 Experimental Results 91 Chapter 7 Conclusions and Future Work 98 7.1 Conclusions 98 7.2 Future Work 99 References 101 Publication Lists 107

    [1] B. Razavi, Design of Integrated Circuits for Optical Communications. John Wiley & Sons, 2012.
    [2] C. Menolfi, T. Toifl, M. Rueegg, M. Braendli, P. Buchmann, M. Kossel, and T. Morf, “A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011, pp. 156–158.
    [3] Y.-H. Song, R. Bai, K. Hu, H.-W. Yang, P. Y. Chiang, and S. Palermo, “A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O transceiver in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1276–1289, May 2013.
    [4] S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1827–1836, Aug. 2014.
    [5] Y. Ogata, Y. Hidaka, Y. Koyanagi, S. Akiya, Y. Terao, K. Suzuki, K. Kashiwa, M. Suzuki, and H. Tamura, “32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2013, pp. 40–41.
    [6] X. Wu, B. Dama, P. Gothoskar, P. Metz, K. Shastri, S. Sunder, J. V. Spiegel, Y Wang, M. Webster, and W. Wilson, “A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2013, pp. 128–129.
    [7] Y.-L. Lee and S.-J. Chang, “A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique,” in Proc. IEEE Int. Symp. Next-Generation Electron., May 2016, pp. 1–2.
    [8] R.-J. Yang, S.-P. Chen, and S.-I. Liu, “A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1356–1360, Aug. 2004.
    [9] J. E. Rogers and J. R. Long, “A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1781–1789, Dec. 2002.
    [10] J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 38, no, 12, pp. 2181–2190, Dec. 2003.
    [11] S. Byun, J. C. Lee, J. H. Shim, K. Kim, and H.-K. Yu, “A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector,” IEEE J. Solid-State Circuits, vol. 41, no, 11, pp. 2566–2576, Nov. 2006.
    [12] J. C. Scheytt, G. Hanke, and U. Langmann, “A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems,” IEEE J. Solid-State Circuits, vol. 34, no, 12, pp. 1935–1943, Dec. 1999.
    [13] B. Razavi, “Challenges in the design of high-speed clock and data recovery circuits,” IEEE Commun. Mag., vol. 40, no. 8, pp. 94–101, Aug. 2002.
    [14] C. Hogge, “A self correcting clock recovery curcuit,” J. Lightwave Technol., vol. 3, no. 6, pp. 1312–1314, Dec. 1985.
    [15] J. Alexander, “Clock recovery from random binary signals,” Electron. Lett., vol. 11, no. 22, pp. 541–542, Oct. 1975.
    [16] Y.-L. Lee, Y.-C. Chen, S.-J. Chang, and Y.-P. Cheng, “A 0.5-to-4 Gbps continuous-rate clock and data recovery circuit with bidirectional frequency detection,” Int. J. Elect. Eng., vol. 21, no. 6, pp. 243–252, Dec. 2014.
    [17] R. Inti, W. Yin, A. Elshazly, N. Sasidhar, and P. K. Hanumolu, “A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3150–3162, Dec. 2011.
    [18] I. Jung, D. Shin, T. Kim, and C. Kim, “A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 s frequency acquisition time,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no, 7, pp. 1310–1315, July 2011.
    [19] B. Abiri, R. Shivnaraine, A. Sheikholeslami, H. Tamura, and M. Kibune, “A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011, pp. 154–156.
    [20] S. Kim, J. Park, Y. Pu, and K.-Y. Lee, “A low power, wide range VCO with automatic amplitude calibration loop,” in Proc. IEEE Int. Conf. ASIC, Oct. 2009, pp. 455–457.
    [21] W.-R. Yang and W.-Y. Jiang, “A dual-path three-stage VCO with wide tuning range,” in Proc. IEEE Int. Conf. ASIC, Oct. 2007, pp. 542–544.
    [22] M. K. Raja, D. L. Yan, and A. B. Ajjikuttira, “A 1.4-psec jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS,” in Proc. IEEE European Solid-State Circuits Conf., Sept. 2007, pp. 524–527.
    [23] H.-H. Chang, J.-W. Lin, and S.-I. Liu, “A wide-range and fixed latency of one clock cycle delay-locked loop,” in Proc. IEEE Int. symp. Circuits Syst., May 2002, pp. 675–678.
    [24] S. B. Anand and B. Razavi, “A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 432–439, Mar. 2001.
    [25] A. Worapishet and M. Thamsirianunt, “An NMOS inductive loading technique for extended operating frequency CMOS ring oscillators,” in Proc. IEEE Midwest Symp. Circuits Syst., Aug. 2002, pp. I–116–19.
    [26] W.-H. Tu, J.-Y. Yeh, H.-C. Tsai, and C.-K. Wang, “A 1.8 V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO,” in Proc. IEEE Asia-Pacific Conf. ASIC, Aug. 2004, pp. 134–137.
    [27] F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 1, pp. 56–62, Jan. 1999.
    [28] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Nov. 1996.
    [29] M. Ramezani and C. A. T. Salama, “An improved bang-bang phase detector for clock and data recovery applications,” in Proc. IEEE Int. Symp. Circuits Syst., May 2001, pp. 715–718.
    [30] W.-Y. Lee and L.-S. Kim, “A 5.4-Gb/s clock and data recovery circuit using seamless loop transition scheme with minimal phase noise degradation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 11, pp. 2518–2528, Nov. 2012.
    [31] M.-S. Hwang, S.-Y. Lee, J.-K. Kim, S. Kim, and D.-K. Jeong, “A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 144–147.
    [32] Y.-S. Seo, J.-W. Lee, H.-J. Kim, C. Yoo, J.-J. Lee, and C.-S. Jeong, “A 5-Gbit/s clock-and data-recovery circuit with 1/8-rate linear phase detector in 0.18-um CMOS technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 6–10, Jan. 2009.
    [33] G. Shu, W.-S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp. 150–151.
    [34] S. Huang, J. Cao, and M. M. Green, “An 8.2-to-10.3 Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2014, pp. 152–153.
    [35] R.-J. Yang, K.-H. Chao, and S.-I. Liu, “A 200-Mbps∼ 2-Gbps continuous-rate clock-and-data-recovery circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 842–847, Apr. 2006.
    [36] S.-H. Lin and S.-I. Liu, “Full-rate bang-bang phase/frequency detectors for unilateral continuous-rate CDRs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 12, pp. 1214–1218, Dec. 2008.
    [37] D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2713–2725, Dec. 2005.
    [38] J. Park and W. Kim, “An auto-ranging 50-210 Mb/s clock recovery circuit with a time-to-digital converter,” in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1999, pp. 350–351.
    [39] R.-J. Yang, K.-H. Chao, S.-C. Hwu, C.-K. Liang, and S.-I. Liu, “A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1380–1390, June 2006.
    [40] I. Jung, D. Shin, T. Kim, and C. Kim, “A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 10, pp. 773–777, Oct. 2009.
    [41] J. Han, J. Yang, and H.-M. Bae, “Analysis of a frequency acquisition technique with a stochastic reference clock generator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 6, pp. 336–340, June 2012.
    [42] C.-L. Hsieh and S.-I. Liu, “A 1–16-Gb/s wide-range clock/data recovery circuit with a bidirectional frequency detector,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 8, pp. 487–491, Aug. 2011.
    [43] Y.-L. Lee, S.-J. Chang, R.-S. Chu, Y.-Z. Lin, Y.-C. Chen, G. J. Ren, and C.-M. Huang, “A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2012, pp. 141–144.
    [44] C.-F. Liang, S.-C. Hwu, and S.-I. Liu, “A jitter-tolerance-enhanced CDR using a GDCO-based phase detector,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1217–1226, May 2008.
    [45] C.-F. Liang, H.-L. Chu, and S.-I. Liu, “10-Gb/s inductorless CDRs with digital frequency calibration,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 9, pp. 2514–2524, Oct. 2008.
    [46] C.-L. Hsieh, H.-L. Chu, and S.-I. Liu, “A 10Gb/s inductorless quarter-rate clock and data recovery circuit in 0.13 um CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 165–168.
    [47] G. Gutierrez and S. Kong, “Unaided 2.5 Gb/s silicon bipolar clock and data recovery IC,” in Porc. IEEE Radio Frequency Integr. Circuits Symp., June 1998, pp. 173–176.
    [48] C. He and T. Kwasniewski, “Bang-Bang CDR's acquisition, locking, and jitter tolerance,” in Proc. IEEE Canadian Conf. Elect. Comput. Eng., Apr. –May 2012, pp. 1–4.
    [49] J. Lee, K. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571–1580, Sept. 2004.
    [50] Y. Sun and H. Wang, “Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers,” in Proc. IEEE Custom Integr. Circuits Conf., Sept. 2009, pp. 343–346.
    [51] D. Hong and K.-T. Cheng, “Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links,” in Proc. IEEE VLSI Test Symp., Apr. 2008, pp. 17–22.
    [52] T. Fujibe, M. Suda, K. Yamamoto, Y. Nagata, K. Fujita, D. Watanabe, and T. Okayasu, “Dynamic arbitrary jitter injection method for≫ 6.5 Gb/s SerDes testing,” in Proc. IEEE Int. Test Conf., Nov. 2009, pp. 1–10.
    [53] L. Liu and E. Lew, “Periodic Jitter Amplitude Calibration with Walking Strobe,” in Proc. IEEE Int. Test Conf., Oct. 2006, pp. 1–8.
    [54] J. E. Jaussi, G. Balamurugan, J. Kennedy, F. O'Mahony, M. Mansuri, R. Mooney, B. Casper, and U.-K. Moon, “In-situ jitter tolerance measurement technique for serial I/O,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 2008, pp. 168–169.
    [55] Y.-C. Huang, P.-Y. Wang, and S.-I. Liu, “An all-digital jitter tolerance measurement technique for CDR circuits,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 3, pp. 148–152, Mar. 2012.
    [56] E. Cheng, J. Kho, Y. L. Tan, W. W. Lo, and M. O. Wong, “Jump the Q: A fast jitter tolerance measurement method using Q-statistical model,” in Proc. IEEE Elect. Design Advanced Package Sys. Symp., Dec. 2010, pp. 1–4.
    [57] S. Kim, M. Kapur, M. Meghelli, A. Rylyakov, Y. Kwark, and D. Friedman, “45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence],” in Proc. IEEE Custom Integr. Circuits Conf., Sept. 2003, pp. 313–316.
    [58] M. A. Kossel and M. L. Schmatz, “Jitter measurements of high-speed serial links,” IEEE Des. Test., vol. 21, no. 6, pp. 536–543, Nov.–Dec. 2004.
    [59] T. Lee, Y. H. Kim, J. Sim, J. S. Park, and L. S. Kim, “A 5-Gb/s 2.67-mW/Gb/s digital clock and data recovery with hybrid dithering using a time-dithered delta–sigma modulator,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no, 4, pp. 1450–1459, Apr. 2016.
    [60] G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 1036–1047, Apr. 2014.
    [61] T. Lee, Y. H. Kim, and L.S. Kim, “A 5-Gb/s digital clock and data recovery circuit with reduced dco supply,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no, 1, pp. 380–384, Jan. 2017.
    [62] M. S.A. Jalali, A. Sheikholeslami, M. Kibune, and H. Tamura, “Reference-less single-loop half-rate binary CDR,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2037–2047, Sep. 2015.
    [63] K. H. Pyun, D. H. Kwon, and W. Y. Choi, “A 3.5/7.0/14-Gb/s Multi-Rate Clock and Data Recovery Circuit With a Multi-Mode Rotational Binary Phase Detector,” in Proc. IEEE Asia Pacific Conf. Circuits Syst., Oct. 2016, pp. 327–329.

    下載圖示 校內：2020-02-21公開
    校外：2020-02-21公開
    QR CODE