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研究生: 黃郁喬
Huang, Yu-Chiao
論文名稱: 以灰階演算法對電子顯微鏡埋藏結構之形貌重建
Morphology Reconstruction of Buried Structures in Scanning Electron Microscopy Using Grey-Level Algorithms
指導教授: 李文熙
Lee, Wen-Hsi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 中文
論文頁數: 123
中文關鍵詞: 掃描式電子顯微鏡(SEM)深度學習三維形貌重建非破壞檢測晶圓缺陷分析
外文關鍵詞: Scanning Electron Microscopy (SEM), Deep Learning, 3D Morphology Reconstruction, Non-Destructive Inspection, Wafer Defect Analysis
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  • 掃描式電子顯微鏡(SEM)由於其高解析度,被廣泛用於觀察微觀結構。為了分析 SEM 影像中的細節結構,我們可以使用深度學習神經網絡進行精確的估測。要訓練這些神經網絡,我們需要大量的訓練資料集,包括 SEM 影像以及其對應的微觀結構。然而,SEM 成像成本高、程序複雜,且受樣本條件限制,這些因素阻礙了神經網絡在大規模缺陷檢測上的應用。為了克服這些挑戰,我們使用 Nebula 模擬 SEM 影像,以生成合成的 SEM 圖像及其對應的深度圖,從而構建一個用於缺陷檢測的訓練資料集。在我們的方法中,Blender 被用來建立 3D 模型並生成三角網格,這些網格以 *.tri 檔的形式表示,包含了模型的幾何資訊與深度資訊。
    這些網格接著被輸入至 Nebula 蒙地卡羅模擬器,以產生 SEM 影像,從 Blender 中提取的深度圖則作為監督式學習的真實標籤(ground truth)。我們在這些合成影像與深度圖上訓練一個以 ResNet 為骨幹的 CNN 模型,以擷取深度變化的特徵並自動識別潛在的缺陷區域。由於表面缺陷通常呈現明顯的深度異常,我們的方法提升了缺陷檢測的準確率與效率。透過將 SEM 模擬與深度學習相結合,我們的方法減少對真實 SEM 影像的依賴,並為晶圓檢測及其他高解析度缺陷分析應用於半導體製造領域提供了一個具成本效益且高效率的解決方案。

    This study proposes a grey-level algorithm-assisted SEM framework for reconstructing buried structures in advanced semiconductor devices. By combining Monte Carlo simulation, BSE signal analysis, and deep learning with ResNet-UNet architecture, the system predicts 3D morphology from single SEM images. The model incorporates atomic number-weighted grey-level mapping and multi-angle image analysis to enhance depth estimation accuracy, particularly for high-aspect-ratio features and subsurface defects.
    The results demonstrate strong agreement between simulation and experimental data, validating the model’s accuracy in interface detection and defect profiling. This method offers a non-destructive, cost-efficient solution for nanoscale inspection, suitable for integration into industrial metrology workflows.

    AbstractII 誌謝VIII 目錄 IX 表目錄 XII 圖目錄 XIII 1 第一章 緒論 1 1-1 先進CMOS元件 1 1-1-1 先進CMOS元件與三維結構特性 1 1-1-2 缺陷對元件性能的影響 3 1-2 缺陷檢測技術簡介 5 1-2-1 Optical Inspection 光學檢測法 6 1-2-2 E-beam Inspection 電子束檢測 7 1-2-3 SEM 與 FIB-SEM 技術 8 1-2-4 背向散射電子訊號於原子序對比與異質材料檢測之應用 8 1-2-5 基於立體視差法之微觀結構 3D 重建技術應用 9 1-2-6 缺陷辨識自動化的發展 10 1-3 微缺陷分析中的掃描式電子顯微鏡應用 10 1-3-1 SEM 原理簡述 11 1-3-2 SEM 影像特性 11 1-3-3 二維 SEM 影像解讀挑戰 11 1-4 研究動機與問題定義 12 1-4-1 以二維為基礎之缺陷檢測方法的侷限 15 1-4-2 從 SEM 影像進行三維重建的機會與潛力 15 1-4-3 研究缺口與目標 15 2 第二章 文獻回顧 17 2-1 SEM影像深度資訊的擷取與三維重建技術 17 2-1-1 基於 SE/BSE 訊號與模擬技術之深度估測方法 17 2-1-2 多視角與步階 SEM 影像於立體重建之應用 18 2-2 SEM 影像於缺陷預測與分類應用之研究 19 2-2-1 側壁粗糙度與缺陷幾何預測模型 19 2-2-2 半導體缺陷分類之深度學習系統 20 2-3 深度學習於 SEM 深度估測與建模應用 20 2-3-1 傳統三維重建方法之限制 20 2-3-2 基於 CNN 之單目深度預測模型 21 2-3-3 結合生成模型之三維建構技術 21 2-4 非破壞式 SEM 成像於多層與埋藏結構之原子序對比分析 21 3 第三章 實驗設計 23 3-1 SEM影像數據取得與模擬 23 3-2 深度學習模型建構與訓練流程 24 3-3 模型應用與效能評估 25 3-4 埋藏結構分析架構訓練流程 26 4 第四章 研究方法 28 4-1 冷場發射掃描式電子顯微鏡(CFE-SEM) 28 4-2 背向散射電子(BSE)訊號分析 29 4-3 電子束能量調變分析 30 4-4 SEM 模擬平台 NEBULA 30 4-5 斜面側牆樣本分析 31 4-6 白光干涉儀應用 31 4-7 晶片三維結構建模 32 4-8 三角網格轉換(Triangulation) 33 4-9 深度圖生成 33 4-10 深度圖轉換為3D物件 34 4-11 大規模資料批次產生 35 4-12 使用Nebula模擬SEM影像 36 4-13 SEM影像平滑化處理 40 4-14 CNN深度預測模型設計 41 4-14-1 CNN 訓練資料的資料增強(Data Augmentation) 42 4-14-2 ResNet 用於深度估測 42 4-14-3 實際 SEM 影像微調(Fine-Tuning) 44 4-15 埋藏結構分析 45 4-15-1 灰階映射與深度推估演算法 46 4-15-2 傾斜角觀測應用於缺陷估測 49 5 第五章 實驗結果與討論 50 5-1 電子束能量對結構辨識能力之影響 50 5-1-1 垂直側壁的深度辨識能力 50 5-1-2 垂直側壁的深度辨識能力 53 5-2 側向偵測器於側壁結構成像之應用 57 5-3 SiGe樣品成像分析 62 5-3-1 電子束能量對BSE訊號的影響 62 5-3-2 不同 BSE 偵測器的影像特性 66 5-3-3 不同倍率下樣品區域的成像分析 66 5-3-4 機器學習模型的資料準備 71 5-3-5 輪廓分析 73 5-4 表面形貌深度預測-實驗設定與定性結果 74 5-5 埋藏結構分析架構預測結果 75 5-5-1 埋藏結構灰階演算法分析 76 5-5-2 傾斜拍攝缺陷的尺寸推算結果 91 6 第六章 結論與未來展望 99 6-1 結論 99 6-2 未來展望 101 參考文獻 102

    [1] Q. Zhang, Y. Zhang, Y. Luo, and H. Yin, “New structure transistors for advanced technology node CMOS ICs,” National Science Review, vol. 11, no. 3, 2024.
    [2] J. Teshima and J. J. Clarke, “From transistors to bumps: Preparing SEM cross-sections by combining site-specific cleaving and broad ion beam milling,” Hitachi High Technologies, Clarksburg, MD, Tech. Paper
    [3] Y. Y. Illarionov et al., “Process implications on the stability and reliability of 300 mm FAB MoS₂ field-effect transistors,” npj 2D Materials and Applications, vol. 8, no. 1, p. 8, 2024.
    [4] A. Jalilvand et al., “Gate-oxide-short defect analysis and fault modeling in FinFETs”, IEEE TCAD, 2020
    [5] K. Cheng et al., “3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications”, 2012.
    [6] H. Radamson et al., “State of the Art and Future Perspectives in Advanced CMOS Technology”, Nanomaterials, 2020.
    [7] Q. Zhang et al., “Optimization of structure and electrical characteristics for four-layer vertically-stacked horizontal gate-all-around Si nanosheets devices,” unpublished, 2024.
    [8] J. Hu, T. Liu, P. Ji, G. Zhang, Y. Huang, C. F. Cheung, and S. Yang, “High‑sensitivity, high‑throughput inspection of nanoscale defects using a laser confocal positioning‑assisted darkfield imaging system,” unpublished.
    [9] Which Electron Detector is Right for Your Application?, SEM Tech Blog, Scanning Electron Microscopy, Thermo Fisher Scientific. [Online]. Available: https://www.thermofisher.com/blog/microscopy/which-electron-detector-is-right-for-your-application/
    [10] D. Samak, A. Fischer, and D. Rittel, “3D reconstruction and visualization of microstructure surfaces from 2D images,” Laboratory for CAD & Lifecycle Engineering, Technion–Israel Institute of Technology, Haifa, Israel, Tech. Rep., 2007.
    [11] Logic and Memory Applications in Semiconductor and Electronics, ZEISS Microscopy. [Online]. Available: https://www.zeiss.com/microscopy/us/applications/semiconductors-electronics/logic-memory.html
    [12] Liao, S., et al. "First demonstration of monolithic CFET inverter at 48nm gate pitch toward future logic technology scaling." 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024.
    [13] HOUBEN, Tim, Huisman, T.: Pisarenco, M.; Van Der Sommen, F,; PHN de With. Depth estimation from a single SEM image using pixel-wise fine-tuning with multimodal data. Machine Vision and Applications, 2022, 33.4: 56.
    [14] VAN KESSEL, L. C. P. M.; HAGEN, C. W. Nebula: Monte Carlo simulator of electron–matter interaction. SoftwareX, 2020, 12: 100605.
    [15] GODARD, Clément, Aodha O. M.; Firman, M.; Brostow, G. J. Digging into self-supervised monocular depth estimation. In: Proceedings of the IEEE/CVF International Conference on Computer Vision. 2019. p. 3828-3838.
    [16] BINNIG, Gerd; QUATE, Calvin F.; GERBER, Ch. Atomic force microscope. Physical Review Letters, 1986, 56.9: 930.
    [17] GAUVIN, Raynald. Review of transmission electron microscopy for the characterization of materials. Materials Characterization and Optical Probe Techniques: A Critical Review, 1997, 10291: 196-225.
    [18] DEN BOEF, Arie J. Optical metrology of semiconductor wafers in lithography. In: International Conference on Optics in Precision Engineering and Nanotechnology (icOPEN2013). SPIE, 2013. p. 57-65.
    [19] GOODFELLOW, Pouget-Abadie, J.; Mirza, M.; Xu, B.; Warde-Farley, D.; Ozair, S.; Courville, A.; Bengio. Y. Generative adversarial nets. Advances in Neural Information Processing Systems, 2014, 27.
    [20] KINGMA, Diederik P.; Welling, M. Auto-encoding variational bayes. arXiv preprint arXiv:1312.6114. 2013.
    [21] Atomic number and crystallographic contrast images with the SEM: a review of backscattered electron techniques, Cambridge University Press, published 05 July 2018.
    [22] M. Čalkovský, E. Müller, and D. Gerthsen, “Quantitative analysis of backscattered-electron contrast in scanning electron microscopy,” Journal of Microscopy, vol. 288, no. 1, pp. 33–44, Jan. 2023, doi: 10.1111/jmi.13148.
    [23] VERDUIN, T.; LOKHORST, S. R.; HAGEN, C. W. GPU accelerated Monte-Carlo simulation of SEM images for metrology. In: Metrology, Inspection, and Process Control for Microlithography XXX. SPIE, 2016. p. 122-135.
    [24] THIBAULT Lechien, Enrique Dehaerne, Bappaditya Dey, Victor Blanco, Sandip Halder, Stefan De Gendt, Wannes Meert 2023 Automated Semiconductor Defect Inspection in Scanning Electron Microscope Images: a Systematic Review 2308.08376
    [25] SAKAKIBARA M, Suzuki M, Tanimoto K, Sohda Y, Bizen D and Nakamae K: Impact of secondary electron emission noise in SEM Microscopy 68 279–88 (2019)
    [26] NAKAMAE K, Fujioka H and Ura K Measurements of deep penetration of low-energy electrons into metal-oxide-semiconductor structure J. Appl. Phys. 52 1306–8 (1981)
    [27] BUNDAY, B., Solecky, E., Vaid, A., Bello, A.F., Dai, X.: Metrology capabilities and needs for 7 nm and 5 nm logic nodes. In: Metrology, Inspection, and Process Control for Microlithography XXXI, vol. 10145, p. 101450 (2017).
    [28] HENAO-LONDOÑO, J.C., Riaño-Rojas, J.C., Gómez-Mendoza, J.B., Restrepo-Parra, E.: 3D stereo reconstruction of SEM images. Modern Appl. Sci. 12(12), 57 (2018).
    [29] WANG, T.-C., Liu, M.-Y., Zhu, J.-Y., Tao, A., Kautz, J., Catanzaro, B.: High-resolution image synthesis and semantic manipulation with conditional GANs. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, pp. 8798–8807 (2018)
    [30] VLADÁR, A.E., Villarrubia, J.S., Chawla, J., Ming, B., Kline, J.R., List, S., Postek, M.T.: 10 nm three-dimensional CD-SEM metrology. In: Metrology, Inspection, and Process Control for Microlithography XXVIII, vol. 9050 (April 2014), p. 90500 (2014).
    [31] EIGEN, D., Puhrsch, C., and Fergus, R.: Depth map prediction from a single image using a multi-scale deep network. In: Advances in Neural Information Processing Systems, pp. 2366-2374, (2014).
    [32] LIU, F., Shen C., and Lin, G.: Deep convolutional neural fields for depth estimation from a single image. In: IEEE Conf. on Computer Vision and Pattern Recognition, pp. 5162-5170, (2015)
    [33] Arat, K. T., Bolten, J., Zonnevylle, A. C., Kruit, P., & Hagen, C. W. (2014). Estimating Step Heights from Top-Down SEM Images.
    [34] Desai, V., & Reimer, L. (1989). Calculation of the Signal of Backscattered Electrons Using a Diffusion Matrix from Monte Carlo Calculations. Physikalisches Institut, Universitat Miinster, Miinster, Federal Republic of Germany.
    [35] Arat, K. T., & Zonnevylle, A. C. (2013). Verification of height and sidewall angle SEM metrology accuracy using Monte Carlo simulation.
    [36] Houben, T., Huisman, T., Pisarenco, M., van der Sommen, F., & de With, P. (2022). Training procedure for scanning electron microscope 3D surface reconstruction using unsupervised domain adaptation with simulated data. Journal of Electronic Imaging, 31(4), 043502.
    [37] van Kessel, L., Huisman, T., & Hagen, C. W. (2020). Understanding the influence of 3D sidewall roughness on observed line-edge roughness in scanning electron microscopy images. Proceedings of SPIE, 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 113250Z. https://doi.org/10.1117/12.2550240
    [38] Sweeney, T., Coleman, S., & Kerr, D. (2022). Deep learning for semiconductor defect classification. 2022 IEEE 20th International Conference on Industrial Informatics (INDIN), 1–6. https://doi.org/10.1109/INDIN51773.2022.9976162
    [39] B. Chakrabarti et al., “A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit”, Scientific Reports, 2017
    [40] X. Wu et al., “B-open defect: A Novel Defect Model in FinFET Technology”, IEEE VTS, 2021.
    [41] H. H. Radamson et al., “The Challenges of Advanced CMOS Process from 2D to 3D,” Applied Sciences, vol. 7, no. 10, p. 1047, Oct. 2017. [Online]. Available: https://doi.org/10.3390/app7101047
    [42] Q. Zhang et al., “Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices,” ResearchGate, [Online]. Available: https://www.researchgate.net/publication/349832007_Optimization_of_Structure_and_Electrical_Characteristics_for_Four-Layer_Vertically-Stacked_Horizontal_Gate-All-Around_Si_Nanosheets_Devices [Accessed: Jun. 10, 2025].
    [43] FinFET to GAA MBCFET: A Review and Insights, IEEE Access, vol. PP, no. 99, pp. 1–1, Jan. 2024, doi: 10.1109/ACCESS.2024.3384428.
    [44] J. Lim, J. Lee, and C. Shin, “Probabilistic artificial neural network for line-edge-roughness-induced random variation in FinFET,” IEEE Access, vol. 9, pp. 86786–86794, Jun. 2021, doi: 10.1109/ACCESS.2021.3088461.
    [45] G. Espiñeira, D. Nagy, G. Indalecio, A. J. García-Loureiro, K. Kalna, and N. Seoane, “Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET,” IEEE Electron Device Letters, early access, doi: 10.1109/LED.2019.2900494.
    [46] G. E. Lloyd, “Atomic number and crystallographic contrast images with the SEM: a review of backscattered electron techniques,” Microscopy and Microanalysis, vol. 24, no. 5, pp. 1–20, Jul. 2018. doi: 10.1017/S1431927618000434.

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