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研究生： 黃詩雄
Huang, Shin-Syong
論文名稱： 高速導管式類比至數位轉換器之設計
Design of High-Speed Pipelined Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 127
中文關鍵詞： 導管式 、管線式 、類比至數位轉換器 、高速 、低功率
外文關鍵詞： pipelined ADC, ADC, A/D, analog-to-digital converter, high speed, low power
相關次數： 點閱：106  下載：12 
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    • 導管式類比至數位轉換器具有高速與高解析度的特性，並且普遍應用在無線通訊、視訊以及數位訊號處理系統中。由於互補式金氧半(CMOS)製程的演進，金氧半場效電晶體的通道長度縮小並且可達到較高的截止頻率，然而，逐漸降低的電源供應電壓使運算放大器的設計變得困難。在本論文中，我們以1.2伏特的電源供應電壓，研製了兩個高速低功率的導管式類比至數位轉換器。
    在第一個設計中，我們以台積電標準90奈米1P9M CMOS製程設計並實作了一個10位元、每秒100百萬次取樣、1.2伏特電源供應電壓的導管式類比至數位轉換器。此類比至數位轉換器採用了偽差動式AB類疊接運算放大器。量測結果顯示在每秒100百萬次取樣下，功率消耗為5.93毫瓦。在每秒100百萬次取樣下量測所得的微分非線性誤差、積分非線性誤差分別是-0.44~0.46 LSB、-0.71~1.12 LSB。在0.5百萬赫茲的輸入訊號下，得到最大的訊號雜訊失真比、無雜訊影響動態範圍分別為54.71分貝、68.6分貝，有效位元則為8.8位元。有效輸入頻寬則大於35百萬赫茲。在較高的取樣頻率下，每秒150百萬次取樣，得到最大的訊號雜訊失真比、無雜訊影響動態範圍分別為50.68分貝、66.51分貝。在每秒100百萬次取樣下此類比數位轉換器的FOM為133 fJ/conversion-step。晶片面積為0.932平方毫米，核心電路面積則為0.235平方毫米。量測結果顯示此類比至數位轉換器具有高功率效率及高速操作的特性。
    在第二個設計中，我們提出一個12位元、每秒100百萬次取樣、1.2伏特電源供應電壓的電荷幫浦式導管式類比至數位轉換器，其並配合了前景式數位校正技術。此類比至數位轉換器以台積電標準90奈米1P9M CMOS製程設計及製造。電容不匹配限制了高解析度的導管式類比至數位轉換器的效能。因此，我們提出了兩個電荷幫浦式導管式轉換級，其具有對電容不匹配不敏感的特性，並且具有將每級1.5位元的轉換器的回授因子從1/2提升到1的優點。此外，我們採用背景式數位校正去校正轉換級的增益誤差，此校正演算法則以MATLAB實現。量測結果顯示，在輸入訊號頻率為0.5百萬赫茲、每秒50百萬次取樣下，所得到的訊號雜訊失真比在校正前與校正後分別為16.21分貝與33.24分貝，功率消耗為13毫瓦。晶片面積為1.538平方毫米，核心電路面積則為0.503平方毫米。

    Pipelined analog-to-digital converters (ADCs) are generally regarded as the A/D converters with high-speed and medium-to-high-resolution characteristics, and they are widely adopted in wireless communication, video and digital-signal-processing (DSP) systems. Thanks to the evolution of the CMOS process, the channel length of MOS transistor is getting smaller, and its unit-gain transition frequency is getting higher. However, the lower supply voltage makes the op-amp design more difficult. In this thesis, we design and implement two high-speed and low-power pipelined ADCs with a 1.2-V supply voltage.
    In the first work, a 10-bit 100-MS/s 1.2-V pipelined ADC has been carried out with TSMC standard 90-nm 1P9M CMOS process. This ADC adopts pseudo-differential class-AB telescopic cascode op-amp. Measurement results show that when the sampling frequency is 100 MS/s, the power consumption is 5.93 mW. The measured DNL and INL are within -0.44~0.46 LSB and -0.71~1.12 LSB at 100MS/s, respectively. The peak SNDR and SFDR are 54.71 and 68.6 dB at a 0.5-MHz input frequency, respectively. The ENOB is 8.8 bit. The ERBW is over 35 MHz. For higher sampling frequency, 150 MS/s, the peak SNDR and SFDR are 50.68 and 66.51 dB, respectively. The FOM of this ADC at 100 MS/s is 133 fJ/conversion-step. The chip area is 0.932mm2, and the active area is 0.235 mm2. The measured results demonstrate high power efficiency and high-speed potential of this ADC.
    In the second work, a 12-bit 100-MS/s 1.2-V charge-pump-based pipelined ADC with foreground calibration has been proposed. It has been designed and implemented with TSMC standard 90-nm 1P9M CMOS process. The performance of a high-resolution pipelined ADC is mainly limited by the capacitor mismatch. Accordingly, we propose two charge-pump-based pipelined stages which are less sensitive to the capacitor mismatch, and the feedback factor of the 1.5-bit/stage MDAC is enhanced from 1/2 to 1. The foreground calibration, which is implemented in MATLAB, is used to correct the stage-gain error of pipelined stages. The measured results show that, with a 0.5-MHz sine wave and operating at 50 MS/s, the SNDR is 16.21 dB and 33.24 dB before and after calibration, respectively, and the power consumption is 13 mW. The chip area is 1.538 mm2, and the active area is 0.503 mm2.

    摘要 I Abstract III Table of Contents VII List of Figures X List of Tables XIV Chapter 1 Introduction 1 1.1 MOTIVATION AND REVIEW OF PIPELINED ADCS 1 1.2 THESIS ORGANIZATION 6 Chapter 2 Fundamentals of Pipelined ADC 7 2.1 ADC PERFORMANCE METRICS 7 2.1.1 Resolution 7 2.1.2 Accuracy 8 2.1.3 Signal to Noise Ratio (SNR) 8 2.1.4 Signal to Noise + Distortion Ratio (SNDR) 10 2.1.5 Dynamic Range (DR) 10 2.1.6 Spurious Free Dynamic Range (SFDR) 11 2.1.7 Offset Error, Linearity Error, Gain Error and Missing Code 12 2.1.8 DNL and INL 13 2.2 REVIEW OF ADC ARCHITECTURES 14 2.2.1 Flash ADC 14 2.2.2 Two-Step ADC (or Subranging ADC) 16 2.2.3 Successive Approximation ADC (SAR ADC) 17 2.2.4 Pipelined ADC 19 2.2.5 Cyclic ADC (or Algorithmic ADC) 20 2.3 SIGNAL CONVERSION AND TIMING ANALYSIS OF PIPELINED ADCS 21 2.3.1 Signal Conversion of Pipelined ADCs 21 2.3.2 Timing Analysis of Pipelined ADCs 23 2.4 DIGITAL ERROR CORRECTION 24 2.4.1 Digital Error Correction and Redundancy 24 2.4.2 1.5-Bit Pipelined Stage 26 2.5 ERROR SOURCES AND NON-IDEALITIES IN PIPELINED STAGES 30 2.5.1 Errors in Sub-ADC 30 2.5.2 Non-idealities in MOS Switches 30 2.5.3 Non-idealities in Op-amp 32 2.5.3.1 Op-amp Input Offset 32 2.5.3.2 Finite Open-Loop DC gain (Finite Gain) 33 2.5.3.3 Non-Linear Open-Loop DC gain 35 2.5.3.4 Finite Unity-Gain Frequency and Slew Rate 36 2.5.4 Capacitor Mismatch 38 2.5.5 Non-Linear Capacitance 39 2.5.6 Noise 39 2.5.6.1 KT/C Noise 39 2.5.6.2 Op-amp Induced Noise 40 Chapter 3 A 10-bit 100-MS/s Pipelined ADC 42 3.1 ADC ARCHITECTURE 42 3.2 FRONT-END DESIGN 43 3.2.1 Front-End Sample-and-Hold Amplifier 43 3.2.2 Bootstrapped Switch 45 3.3 CAPACITOR VALUE DETERMINATION 47 3.3.1 Noise 47 3.3.1.1 MDAC Input-Referred Noise 48 3.3.1.2 SHA Input-Referred Noise 48 3.3.1.3 Total Input-Referred Noise 49 3.3.2 Capacitor Matching 50 3.4 OP-AMP AND COMMON-MODE STABILIZATION SCHEME 54 3.4.1 Pseudo-differential Class-AB Telescopic Cascode Op-amp 54 3.4.2 Specification Requirement of Op-amp 58 3.4.3 Common-Mode Stabilization Scheme 61 3.4.4 Bias Circuit 66 3.5 MULTIPLYING D/A CONVERTER (MDAC) 67 3.6 COMPARATOR 68 3.6.1 Dynamic Latch Comparator [59] 68 3.6.2 Switch-Capacitor Comparator [46] 70 3.7 1.5-BIT SUB-ADC AND 2-BIT FLASH ADC 72 3.8 DIGITAL ERROR CORRECTION AND DELAY ELEMENTS 73 3.9 LAYOUT AND FLOOR PLAN 75 3.10 SIMULATION RESULTS OF 10-BIT 100-MS/S ADC 76 3.11 EXPERIMENTAL RESULTS 82 3.12 SUMMARY 88 Chapter 4 A 12-bit 100-MS/s 1.2-V Charge-Pump-Based Pipelined ADC 89 4.1 ARCHITECTURE OF PROPOSED ADC 89 4.2 SHA-LESS FRONT-END DESIGN 91 4.3 NEW STRUCTURES FOR MULTIPLY-BY-TWO GAIN STAGE [67] 94 4.4 PROPOSED CHARGE-PUMP-BASED MDAC 97 4.4.1 Proposed Charge-Pump-Based MDAC 97 4.4.2 Dynamic Range Doubling (DRD) [71] 99 4.4.3 Feedback Factor and CM Rejection 101 4.4.4 Proposed Charge-Pump-Based MDAC with Bottom-Plate Sampling 103 4.4.5 Transfer Function of Proposed MDAC 104 4.4.6 Digital Foreground Calibration [72] 105 4.5 DETAIL OF PROPOSED PIPELINED ADC 106 4.6 LAYOUT AND FLOOR PLAN 107 4.7 TEST SETUP AND EXPERIMENTAL RESULTS 109 4.7.1 Test Setup 109 4.7.2 Experimental Results 112 4.7.3 Fault Diagnosis 113 4.8 SUMMARY 116 Chapter 5 Conclusions and Future Work 117 5.1 CONCLUSIONS 117 5.2 FUTURE WORK 118 Bibliography 119

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