本論文為4.8 GHz鎖相迴路電路設計，應用於高頻訊號合成器系統中做為基頻訊號來源，對於突波表現以及訊號解析度有更高的要求。本論文內容主要分為使用電容陣列之壓控振盪器以及小數型鎖相迴路的理論、設計與實作結果。壓控振盪器及小數型鎖相迴路均為採用TSMC 0.18μm 1P6M製程實現，並且以on-wafer的方式進行量測。
壓控振盪器為鎖相迴路核心，關乎輸出訊號品質之好壞，本論文中振盪器以電感電容組成之共振腔式壓控振盪器架構，與一般的環形振盪器相比，其優點為優異的相位雜訊表現以及較小的壓控靈敏度；另外採用電容陣列方式拓展頻率可變範圍的同時保有較小的壓控靈敏度，減輕壓控振盪器對於供應電壓之靈敏度，並對於整體鎖相迴突波達到抑制作用。
電感品質因子以及偏壓電流為共振腔壓控振盪器相位雜訊的重要因子，核心電路部分著重於這兩者的設計並對於輸出相位雜訊進行深入探討，使得此壓控振盪器設計中同時具有較好的共振腔負載阻抗特性以及由理論得出最適當的偏壓電流，因此在本論文中的壓控振盪器得以有較好的相位雜訊表現並保有較低的功率消耗。透過模擬之頻率可變範圍介於4.21 GHz至5.24 GHz，量測時介於4.02 GHz至5.24 GHz。相位雜訊模擬時在頻率偏移1 MHz時最佳表現為-124.3 dBc/Hz，而量測時最佳表現為-124.5 dBc/Hz，核心功耗為2.4 mW，輸出功率介於 -2 dBm至 +2 dBm。
非整數型鎖相迴路系統包含子電路如:相位頻率偵測器(Phase frequency detector)、充電泵(Charge pump)、低通濾波器(Low pass filter)、壓控振盪器(Voltage-controlled oscillator)、預除頻器(Pre-scalar)、多模除頻器(Multi-modulus divider)以及三角積分調變器(Delta-sigma modulator)。非整數運算藉由三階三角積分調變器使鎖相迴路操作於不同整數除數之間達成平均的小數除數，由於三角積分器對於系統線性度要求甚高，因此採用動態匹配式充電泵架構，確保上流電流之匹配，並且對於相位頻率偵測器與充電泵對於輸入範圍的線性度進行模擬，得出其近似為二次函數之誤差項。由於低通濾波器之階數必須大於等於三角積分器之階數才得以濾除noise shaping過後集中在高頻的取樣雜訊，因此採用三階的迴路濾波器，也進一步對於輸入突波進行衰減，降低其對於輸出頻譜之影響。
一般來說，壓控振盪器與鎖相迴路其他子電路比較起來相對耗能，本設計中藉由優化電感及偏壓電流，壓低壓控振盪器功耗，另外由於預除頻器為操作速度最高之數位子電路，本論文對於預除頻器電路進行系統性優化，包括架構的選擇以及電晶體的合併，得以提升速度表現及大幅降低預除頻器的功率消耗，以上原因導致鎖相迴路整體系統達到較低的功耗；並且對於預除頻器進行完整的建立時間(setup time)及保持時間(hold time)的模擬，確保其數位運作在高頻下的理論操作極限，提升晶片之良率。
鎖相迴路參考頻率輸入為85.71 MHz，輸出頻率介於4.29 GHz至5.23 GHz，頻率解析度約為5.36 MHz，參考突波強度約為-48.73 dBm，模擬時在頻率偏移量為1 MHz時的相位雜訊表現為 -102.48 dBc/Hz，量測時在頻率偏移量為1 MHz時的相位雜訊表現為 -102.96 dBc/Hz，輸出功率介於-1 dBm至 +2 dBm之間，整體功率消耗為6.6mW。

This thesis can be divided mainly into two parts: the voltage-controlled oscillator (VCO) and the complete system of the fractional PLL. The VCO and the PLL are both fabricated with TSMC 0.18 μm CMOS process.
The VCO possesses a wide tuning range while keeping the K_vco small due to the credit of the capacitor banks. Reducing the K_vco contributes to better phase noise performance and spur level attenuation in the PLL system on account of its loop dynamics. The tuning range of 4.02 GHz ~ 5.24 GHz (26.3%) was measured. The best phase noise performance recorded was -124.5 dBc/Hz at 1 MHz frequency offset. The power consumption of the core circuit is about 2.4 mW, with output power greater than -2 dBm. The chip covers up about 0.69 mm².
The PLL contains a phase and frequency detector (PFD), charge pump (CP), low-pass filter (LPF), voltage-controlled oscillator (VCO), multi-modulus divider (MMD) and a delta-sigma modulator (DSM). The PLL achieves fractional dividends by DSM modulating MMD. The reference frequency is set to be 85.71 MHz and the PLL operates between 4.285 GHz and 5.229 GHz. The best phase noise performance is -102.96 dBc/Hz at 1 MHz frequency offset. The power consumption of the core circuit is 6.6 mW, with output power greater than -2 dBm. The chip covers up about 0.87 mm².

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