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研究生： 許中倫
Hsu, Chung-Lun
論文名稱： 高效率三角積分調變器之設計與實現
Design and Implementation of High Power-Efficient Sigma-Delta Modulators
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 106
中文關鍵詞： 增益增強型伸縮放大器 、雙取樣技術 、增益增強型電流鏡式放大器 、三角積分調變器
外文關鍵詞： gain-enhanced current mirror OPAMP, sigma-delta modulator, double-sampled technique, gain-boosting telescopic OPAMP
相關次數： 點閱：118  下載：4 
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    • 本論文提出兩種三角積分調變器：一個適用於居家型生醫量測儀器，另一個適用於無線通訊領域。對此兩種應用，其訊號頻寬範圍以及調變器架構的考量是截然不同，因此同時從系統架構層面以及電路層面著手，以設計低功率轉換效率的調變器。以下分別描述此兩種三角積分調變器：
    1)一個應用於生醫感測之1.8伏特23微瓦三階三角積分調變器:
    此三角積分調變器使用三階雜訊移頻單位元單迴路架構設計，可忍受部分類比電路的不理想因素。並且，使用增益增強型電流鏡式放大器，以減少整體積分器的功率消耗；並將放大器中的各個電晶體，設計於近弱反轉區，可提升放大器的功率效率。除此之外，等比例調降第二級及第三級積分器的電容值，可再進一步減少功率消耗。
    此三角積分調變器是使用0.18微米製程，1.2伏特供應電壓。從模擬結果得知此當此調變器操作於2千赫茲訊號頻寬、100倍超取樣率時，訊噪比為85-dB ，並消耗功率23微瓦。
    2)一個應用於訊號頻寬、使用雙取樣技術之1.2伏特、95-dB訊噪比、8.3百萬赫茲訊號頻寬的三角積分調變器:
    此三角積分調變器使用低失真全前授單迴路、四位元量化器之四階雜訊移頻架構設計，使積分器只處理量化誤差而不包含輸入訊號，並大幅降低訊號頻帶內的量化誤差，提升整體操作速度。而在電路層面，同時使用高效率雙取樣技術以及增益增強型伸縮放大器，可進一步提升調變器的功率效率；此外，使用資料加權平均演算法，降低數位類比轉換器中不匹配效應。
    此三角積分調變器器是使用低功率1層多晶矽6層金屬線製程設計。從模擬結果得知，此調變器在24倍超取樣率下效能可達到95-dB訊噪比，包含類比及數位電路部分總共消耗53毫瓦。可藉由計算FOM得知功率轉換效率為3×103 pJ/轉換，其效率高於其他已發表的調變器。

    由以上兩個三角積分調變器的驗證結果可知，藉由同時考量系統架構及電路層面，可達到高功率轉換效率的特性，並對生醫感測器以及無線網路通訊領域提供了很好的解決方案。

    In this thesis, two sigma-delta modulators are proposed: one is for home-used human body bio-sensing application, and the other is for wireless communication application. There are quite different considerations in the view points of input signal bandwidth and modulator topology for these two applications. Systematic procedures which focus on both system and circuit levels are emphasized to design the high power efficient modulators. The two sigma-delta modulators are presented as below:
    1)A 1.2-V 23-μW 3rd-order Sigma-Delta Modulator for Bio-Sensing Application:
    The modulator is designed with third-order single-bit single-loop topology because of its low-sensitivities to the analog building blocks’ non-idealities. In the circuit level, the gain-enhanced current mirror OPAMP is adapted to minimize the power consumptions of the integrators. In addition, the transistors in OPAMP are operated near the weak inversion region to achieve higher power efficiency. Furthermore, the sizes of capacitor are scaled down in the second and third integrators for saving more power.
    The simulation results show the SNDR of the sigma-delta modulator is 85-dB with 2-kHz signal bandwidth and 100-X oversampling ratio. Also, it consumes 23-μW from 1.2-V power supply voltage by using a 0.18-μm 1P6M process.
    2)A 1.2-V, 95-dB SNDR, 8.3-MHz Signal-Bandwidth Sigma-Delta Modulator Using Double-Sampled Technique for Wide-Bandwidth Application:
    A four-bit fourth-order sigma-delta modulator is designed with low-distortion full feed-forward single-loop topology. Since each integrator only processes the quantization noise without input signal component, the in-band quantization noise is decreased significantly. Also, the operating speed can be raised. In the circuit level, the high-efficiency double-sampled technique and gain-boosting telescopic OPAMP are adopted to further raise the power efficiency. Moreover, the data weighted averaging algorithm is used to suppress the mismatching effect in the digital-to-analog converter.
    The sigma-delta modulator is implemented in 1P6M Low-Power technology. From the simulation results, a 95-dB SNDR is achieved with 53-mW total power consumption under 24-X oversampling ratio. The power efficiency of the proposed modulator which is 3×103 pJ/conversion, which is betterer than many published sigma-delta modulators.

    From the above results, the high power efficient sigma-delta modulators are achieved by considering both the system and circuit levels. Hence, the proposed modulators are excellent choices for bio-sensing and wireless communication applications

    Abstract..............................................................................................................................................i Acknowledgement............................................................................................................................v List of Tables .................................................................................................................................... x List of Figures ................................................................................................................................ xii Chapter 1 Introduction ....................................................................................................................... 1 1.1 Background and Motivation ....................................................................................................... 1 1.2 Organization of the Thesis .......................................................................................................... 3 Chapter 2 Fundamentals of Sigma-Delta Converter ....................................................................... 5 2.1 Introduction of Analog-to-Digital Converter .............................................................................. 5 2.2.1 Nyquist-rate converters ........................................................................................................ 6 2.1.2 Oversampling converters ..................................................................................................... 7 2.2 Sigma-Delta Modulator .............................................................................................................. 8 2.2.1 Oversampling technique ...................................................................................................... 8 2.2.2 Noise-shaping technique .................................................................................................... 11 2.3 Sigma-Delta Modulator Topologies .......................................................................................... 14 2.3.1 Single-loop topology .......................................................................................................... 15 2.3.2 Multi-stage topology .......................................................................................................... 16 2.3.3 Multi-bit quantization topology ......................................................................................... 17 2.4 Summary .................................................................................................................................. 18 Chapter 3 Analysis the Non-ideality in Sigma-Delta Modulator .................................................. 20 3.1 Integrator Leakage .................................................................................................................... 20 3.1.1 The leakage source of integrator ........................................................................................ 21 3.1.2 The integrator with leakage effect ..................................................................................... 22 3.2 Integrator Settling Error ............................................................................................................ 24 3.2.1 The settling error ................................................................................................................ 25 3.2.2 The effects of settling error ................................................................................................ 25 3.3 kT/C Noise in Switched-Capacitor Integrator .......................................................................... 26 3.4 Summary .................................................................................................................................. 27 Chapter 4 A 1.2-V, 85-dB SNDR, 23-μW 3rd-order Sigma-Delta Modulator for Bio-Sensing Application........................................................................................................................................ 28 4.1 Architecture Considerations ...................................................................................................... 29 4.2 Circuit Implementation ............................................................................................................. 32 4.2.1 Integrator ............................................................................................................................ 32 4.2.2 Gain-enhanced current mirror OPAMP ............................................................................. 34 4.2.3 1-bit quantizer design ......................................................................................................... 36 4.2.4 Clock generation ................................................................................................................ 37 4.2.5 Complete circuit diagram ................................................................................................... 38 4.3 Experimental Results ................................................................................................................ 39 4.3.1 Simulation results............................................................................................................... 39 4.3.2 Layout consideration .......................................................................................................... 40 4.3.3 Measurement results .......................................................................................................... 41 4.4 Summary .................................................................................................................................. 45 Chapter 5 A 1.2-V, 95-dB SNDR, 8.3-MHz Signal-Bandwidth Sigma-Delta Modulator Using Double-Sampled Technique for Wide-Bandwidth Application .................................................... 46 5.1 Architecture Considerations ...................................................................................................... 47 5.1.1 Considerations of conventional structure ........................................................................... 47 5.1.2 The full feed-forward structure .......................................................................................... 48 5.1.3 The fourth-order four-bit full feed-forward structure ........................................................ 51 5.2 Double-Sampled Integrator ....................................................................................................... 56 5.2.1 Introduction to double-sampled integrator ......................................................................... 56 5.2.2 The fully-floating double-sampled integrator .................................................................... 59 5.2.3 Design considerations of double-sampled sigma-delta modulator .................................... 61 5.3 Circuit Implementation ............................................................................................................. 66 5.3.1 Integrator ............................................................................................................................ 66 5.3.2 OPAMP .............................................................................................................................. 69 5.3.3 Active adder ....................................................................................................................... 76 5.3.4 Multi-bit quantizer ............................................................................................................. 79 5.3.5 Data weighted averaging (DWA) design ........................................................................... 82 5.3.6 Clock generation diagram .................................................................................................. 86 5.4 Simulation Results and Layout ................................................................................................. 89 5.5 Summary .................................................................................................................................. 93 Chapter 6 Conclusions and Future Work ....................................................................................... 95 6.1 Conclusions ............................................................................................................................... 95 6.2 Future Work .............................................................................................................................. 96

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