近年來，隨著晶片製程的持續發展，不僅讓每單位面積內的電晶體數量穩定上升中，相應的，單位面積內的功率，也稱為功率密度(power density)，不可避免的也持續上升。更高的功率密度會造成晶片的平均溫度上升，而當晶片中的溫度提高時，可能會造成電晶體的漏電流持續上升，進一步的提高溫度，形成惡性循環。這種情況嚴重甚至會造成晶片燒毀的現象，設計者可能必須調降晶片效能以使晶片可以運作。因此，在現代設計中，熱效應的問題越來越顯著，在晶片中消除可能出現的熱點已經成為一個必須考慮的因素。雖過去已有許多著作針對熱效應平面規劃進行研究與探討，但多半採用隨機擾動之演算法，通常耗時甚久，且結果之品質並不穩定。由於上述原因，本論文提出一個考量熱效應並滿足固定框架限制的解析式平面規劃方法，其中大略分為兩個階段。首先於全域分布階段中，透過數學解析法同時最佳化溫度以及繞線長度(wirelength)，讓較熱之模組可以互相遠離，藉此不讓熱堆積以至於產生更高之溫度，而獲得具考量溫度且全域觀的初始分布狀態；接著於局部合法化擺置階段，在不過度影響前一階段結果的前提下，移除掉覆蓋區域以獲得可行的平面規劃結果。由實驗結果顯示，本論文所提出的方法可以在不增加過多的線長前提下，讓整體的溫度進一步的降低。

As advance of the manufacture technology, the number of transistors in a chip increase dramatically. And this also causes the average power density of a chip rise continuously. The high power density results in higher temperature, which may cause more leakage current appearing and a negative feedback occurs. The designers may need to slow down the chip frequency in order to improve chip stability. Therefore, eliminating possible hotspots has become a serious problem in modern IC designs. Although there has been some works focus on thermal aware floorplanning methodology, the main architecture usually based on the simulated annealing algorithm, which is very time consuming. Further, the solution quality is not stable. Hence, this thesis proposes a thermal aware floorplanning methodology based on the analytical approaches. The proposed methodology can be divided into two parts. The first stage optimizes wirelength and while reducing chip temperature at the same time. The second stage removes overlap area to get a feasible floorplan. The experiment results show that our methodology can reduce the peak temperature while not increasing too much wirelength.

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