本論文主要為無線頻率感測接收機前端電路的整合設計與製作，所製作的接收機電路包含操作於2.4 GHz與1 GHz兩頻帶版本。其無線頻率感測接收機電路晶片可運用於相關的感測系統中，如眼壓監控系統(IOP)。晶片製作為使用國家晶片中心(CIC)提供之TSMC 180 nm 1P6M RFCMOS製程。
接收機電路分為兩個區塊：射頻前端接收電路及鎖相迴路。論文中將會介紹兩個區塊中子電路的設計考量及模擬結果，並展示其量測結果。為了完整無線感測接收機電路的量測，此論文也包含了2.4 GHz的PCB天線與阻抗匹配傳輸線的設計及整合量測。
前端接收電路分大致上分為四級；低雜訊放大器(Low Noise Amplifier)、主動式相位切割器(Phase Splitter)、雙平衡混頻器(Double-balanced Mixer)及中頻放大器。在2.4 GHz前端接收電路中，第一級低雜訊放大器需擁有較低的雜訊指數來增加其接收靈敏度；第二級的電流再利用疊接式相位切割器擁有高增益及精確的差動相位輸出；第三級的源極注入混頻器能有效的抑制LO訊號擺幅大小對線性度的影響；第四級的輸出緩衝級設計主要為驅動輸出端負載為考量。2.4 GHz前端接收電路於1.8 V操作電壓下能接收感測訊號功率為-60 dBm的射頻頻率變化。前端電路不包含緩衝器之總功率耗損為7.38 mW。在1 GHz前端接收電路於1.3 V操作電壓下能感測功率為-55 dBm射頻訊號，其功率耗損不包含緩衝器後為8.68 mW。鎖相迴路設計包含相位頻率偵測器（PFD）、電荷幫浦、迴路濾波器、除頻器及壓控振盪器。於900 MHz鎖相迴路中，電感電容共振腔壓控振盪器(LC-tank VCO)擁有較好的相位雜訊，搭配運算放大器回授之電荷幫浦能夠補償使得製程變異下皆有良好的電流匹。搭配低功耗TSPC除頻器，在960 MHz的輸出頻率下相位雜訊於1 MHz偏移頻率為-125.9 dBc/Hz，不包含緩衝器後功率消耗為4.7 mW。

This thesis presents the integration design and chip implementation of two wireless frequency sensing receiver front-end circuits which can operate at 2.4 GHz and 1 GHz, respectively. These receiver front-end circuits can be used for the wireless sensor in intraocular pressure(IOP) systems. Both of the chips are fabricated by CIC in TSMC’s 180 nm 1P6M RF CMOS process.
There are two main function blocks in our designs: RF front-end and phase-locked loop (PLL). In this thesis, we will report the design considerations and simulation results of the sub-circuits in these blocks. The measurement results of the receiver front-end integration will be also shown. Especially, for the completeness sake, the designs of 2.4 GHz on-PCB half-wave dipole antennas with impedance-matching transmission lines are included.
From the measurement results, it is found that the 2.4GHz receiver front-end can detect the RF frequency change with an input signal power level of -60 dBm. Also the 1 GHz receiver front-end circuit operated at 1.3 V supply voltage can detect an input signal level of -55 dBm, and the phase noise of the designed PLL is -125.9 dBc/Hz at 1 MHz offset from the carrier frequency of 960 MHz.

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