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| 研究生： |
林英儒 Lin, Ying-Zu |
|---|---|
| 論文名稱： |
CMOS高速比較器式類比數位轉換器 CMOS High-Speed Comparator-Based Analog-to-Digital Converters |
| 指導教授： |
張順志
Chang, Soon-Jyh |
| 學位類別： |
博士 Doctor |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2010 |
| 畢業學年度： | 98 |
| 語文別： | 英文 |
| 論文頁數： | 89 |
| 中文關鍵詞： | 類比數位轉換器 、資料轉換器 、比較器式 |
| 外文關鍵詞： | ADC, data converter, comparator-based ADC |
| 相關次數： | 點閱：99 下載：27 |
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在這本博士論文之中，我們探討在先進CMOS製程中比較器式類比數位轉換器的發展。比起以放大器為基礎的類比數位轉換器架構，以比較器為基礎的類比數位轉換器有速度與功率效率上的優勢。這份論文提供了理論上的分析與實務上的驗證。本論文以三個主要章節分別探討三種極具高速操作且低功率消耗潛力的架構:快閃式類比數位轉換器、二位元搜尋式類比數位轉換器以及複合式類比數位轉換器。在每個章節中，我們由設計動機開始，繼而介紹轉換器架構與電路方面的設計議題，最後提供晶片的實作以作為理論的佐證。
在快閃式類比數位轉換器的部分，我們提供了快閃式類比數位轉換器的基礎介紹、近年來的主流電路技巧(電阻平均網路、內插法以及數位校正)的定性與定量分析。最後是二個晶片的實作，一個是使用典型設計技巧並且針對消耗功率進行最佳化的架構，另一個使用數位校正以增加精確度。在接下來的章節，我們介紹一種介於快閃式類比數位轉換器與漸近式類比數位轉換器之間的架構:二位元搜尋式類比數位轉換器。這個部分我們分析了創新架構的利基:較少的比較器數目、低功率消耗以及相當快的操作速度。這個部分也提出了一個五位元晶片的實作來驗證架構。第三個部分展示了不同架構類比數位轉換器組合的可能性。每一種類比數位轉換器的架構都有其優缺點存在。藉由不同架構的組合，可以得到截長補短的效果。這個章節提供了一個快閃式與漸近式類比數位轉換器組合的實作。這個架構的優勢在於結合了快閃式的高操作速度與漸近式的低功率消耗。不論從理論的分析與實驗結果均顯示這個架構對於操作速度與線性度上的提昇有顯著的效益。
近年來類比數位轉換器的發展因應單晶片整合的需求，以壓低功率消耗、縮小晶片面積為主要趨勢。本論文所提出的架構上的改善以及電路技巧能達到這二項主要需求，因此這三種架構在主流的類比數位資料轉換應用中，具有相當大的實用性。
This dissertation investigates comparator-based analog-to-digital converters (ADCs) in scaled CMOS technologies. Compared to amplifier-based ones, comparator-based ADCs have better potential in both speed and power efficiency. This dissertation presents not only theoretical analysis but also silicon verification. Three major chapters expound on the recent development of the flash ADC, binary-search ADC, and hybrid ADC designs. Each chapter first describes the motivation and background of each ADC. Then, the subsequent sections illustrate architecture modifications and circuit techniques. Finally, silicon prototypes are given as design examples to demonstrate the effectiveness and efficiency of the proposed techniques.
The flash-ADC part describes the basics of flash ADCs and discusses popular circuit techniques including resistive averaging network, interpolation and digital calibration. Both qualitative and quantitative analyses of these techniques are provided to give readers insights into flash ADC design. This part provides two 5-bit and above 3-GS/s prototypes: The first one is a conventional design with power consumption optimization and the other one uses a digital offset calibration method. In the following chapter, the dissertation presents a new ADC: binary-search ADC. This is an architecture between flash and SAR ADCs. The proposed ADC has a smaller comparator count than a conventional binary-search ADC. A binary-search ADC with a reduced comparator count shows good compromises between hardware, operation speed and power consumption. This chapter uses a 5-bit silicon prototype to demonstrate the high operation speed (800 MS/s) and power efficiency (around 100 fJ/conversion-step) of this ADC. This last part investigates the combinations of different ADC architectures. Since each ADC has its advantages and disadvantages compared to other ones, we can get benefits by combining different ADCs. This part shows the design and implementation of a combination of flash and SAR ADCs. The hybrid ADC consists of a flash coarse ADC and a SAR fine ADC, which exploits the high speed of a flash ADC and low power of a SAR ADC. Both theoretical and silicon results show this ADC improves sampling speed (150 to 200 MS/s) and linearity (> 70-dB SFDR) while still maintaining excellent power efficiency (around 20 fJ/conversion-step).
For system integration, the current design targets for the ADC are low power and small area. The proposed works in this dissertation cover a wide working range in both accuracy (5 to 9 bits) and speed (100 MS/s to 4 GS/s). Due to their excellent power efficiency and small active area, these ADCs are capable of being suitable building blocks in SoC applications.
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校內：2011-08-18公開校外：2012-08-18公開