如今，對嵌入式處理器的需求隨著應用的變化而有所不同，因此處理器架構需要相應地改變，或者需要擴展指令集架構（ISA）。採用RISC作為開源指令集架構的RISC-V處理器已經逐漸成為取代基於ARM處理器的選擇。自從引入LLVM後，它幾乎總是被用來開發新的架構或移植嵌入式系統的編譯器後端。隨著LLVM功能的不斷增加，如何提高編譯器後端的品質和模組化是值得探討的。
本文重點介紹了TableGen工具在LLVM後端架構中的應用，其對目標暫存器和目標指令集.td（target description）檔的描述，以及後端編譯器的構建過程，分析了後端代碼生成過程，並在構建過程中完成了對目標機器系統屬性的描述。由於每個目標架構中的暫存器和指令集的描述都使用了TableGen的語法和結構，在本文最後，可以在現有架構下增加擴展指令集。
最後，本文將以32位元整數RISC-V架構為例，實現暫存器、堆疊佈局、指令描述等；完成組合語言輸出，用模擬器測試，以保證編譯器的準確性。

Nowadays, the demand for embedded processors varies with the application, so the processor architecture needs to be changed accordingly, or the instruction set architecture (ISA) needs to be extended. The RISC-V processor, which uses RISC as the open source instruction set architecture, has gradually become the choice to replace the ARM-based processors. Since the introduction of LLVM, it is almost always used to develop a new architecture or to port the compiler backend of an embedded system. With the increasing functionality of LLVM, it is worthwhile to explore how to improve the quality and modularity of the compiler backend.
In this paper, we focus on the use of the TableGen tool in the LLVM backend architecture, its description of the target registers and the target instruction set file.td (target description), and the construction process of the backend compiler, analyzing the backend code generation process and completing the description of the properties of the target machine system during the construction process. Since the description of registers and instruction sets in each target architecture uses the syntax and structure of TableGen, after this paper, it is possible to add extended instruction sets under the existing architecture.
Finally, in this paper, we will use the 32-bit integer RISC-V architecture as an example to realize the register, stack layout, instruction description, etc.; we will complete the assembly language output and use the simulator to test it to ensure the accuracy of the compiler.

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