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研究生： 郭文軒
Kuo, Wen-Hsuen
論文名稱： 系統整合之高效率協定轉換硬體自動產生器
Efficient Protocol Converter Generation for System Integration
指導教授： 謝明得
Shieh, Ming-Der
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 68
中文關鍵詞： 包裝器 、非同步先進先出緩衝器 、協定轉換器
外文關鍵詞： asynchronous FIFO, wrapper, protocol converter
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    • 隨著系統晶片設計複雜度的上昇且設計時程逐漸地縮短，如何將系統快速整合成為一個具有競爭力的關鍵。由於矽智財(IP)在設計時，並不會考慮到將來會使用在何種匯流排上，因此常需要包裝器(Wrapper)來處理不匹配的介面，而使用不同種類匯流排的系統要整合也需要橋接器(Bridge)來處理介面不匹配，本論文的主旨便在於探討如何快速且考慮系統效能的情況下，自動產生協定轉換器處理協定不匹配的問題。我們提出完整的協定轉換器自動設計流程，並討論透過不同限制條件下，使合成的結果能在系統使用上更有效。此外針對在頻率或相位的不匹配，我們提出改良式非同步先進先出緩衝器(Asynchronous FIFO)，整合協定轉換器並有效的化簡控制電路。最後針對不同匯流排操作速度下，我們提供組合式輸出或暫存器輸出兩種不同的結果，使我們的協定轉換器更具應用彈性。

    As complexity of System-on-Chip keeps increasing and the time to market becomes shorter, how to integrate systems rapidly is an important issue to be competitive. In general, we don’t know which bus an IP (Intellectual Property) would be plugged in when we began to design an IP. Thus we need a wrapper to handle the mismatch between interfaces for integrations. The same problems are also encountered when we want to integrate two systems that use different bus protocols; hence we use a bridge to connect these two buses. In this thesis, we explore methods to generate protocol converters automatically under the consideration of system performance. We also discuss the proposed automatic generation process with different constraints that leads to get more efficient performance. For the frequency/phase mismatch, we proposed a modified asynchronous FIFO together with our protocol converter to simplify system integrations. Finally we support combinational outputs and registered outputs for buses operated at different speeds. This makes our automatic protocol converter generation tool more flexible.

    CONTENTS CONTENTS vi LIST OF TABLES viii LIST OF FIGURES ix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Background 3 2.1 Main Idea 3 2.2 Algorithms of Converter Synthesis 4 2.2.1 Protocol Specification 4 2.2.2 Synthesis Algorithm 5 2.2.3 Converter Synthesis with Constraints 9 2.2.4 Converter of Two Protocols Oprating at Different Clock Frequencies 10 2.3 Protocol Converter Synthesis with FIFO 12 2.3.1 Data Path Considerations 13 2.3.2 Control Synthesis 13 2.3.3 Asynchrous FIFO 15 2.4 Evaluating the Throughput Rate of Synthesized Converters 17 Chapter 3 Proposed Protocol Converter Synthesis Flow 19 3.1 Protocol Specification 20 3.1.1 Commands of Protocol Specification 20 3.1.2 Input Format Checker 26 3.2 Data Path Configurations 29 3.2.1 FIFO in the Same Clock Domain 29 3.2.2 FIFO between Independeant Clock Domains 32 3.2.3 Assignment of the Connection between Data Ports 40 3.3 Synthesis Algorithm 42 3.3.1 Two Protocols Operated in the Same Clock Domain 42 3.3.2 Two Protocols Operated in Independent Clock Domains 43 3.4 RTL Generation 46 3.4.1 Combinational outputs 46 3.4.2 Registered outputs 48 Chapter 4 Implementation Result and Verification 50 4.1 Implementation Result of FIFO Interface 50 4.2 Experiment1 54 4.3 Experiment2 61 4.4 GUI Tool for Automatic Protocol Converter Generation 62 Chapter 5 Conclusion and Future Work 66 References 67

    References
    [1] J. Akella and K. McMillan, “Synthesizing Converter between Finite State Protocols,” in Proc. Int. Conf. Comput. Design, pp.410-413, Oct. 1991.
    [2] P. E. Green, Jr., “Protocol conversion,” IEEE Trans. Commun., vol. COM-34, pp.257-168, Mar. 1986.
    [3] K. L. Calvert and S. S. Lam, “Formal Method for Protocol Conversion,” IEEE Trans. Commun., vol. 8, pp.127-168, Jan. 1990.
    [4] S. S. Lam, “Protocol conversion,” IEEE Trans. Software Eng., vol. 14, pp. 353-362, Mar. 1988.
    [5] K. Okumura, “A formal protocol conversion method,” in Proc. ACM Conf. on Communications architectures and protocols, pp.30-37, Aug. 1986.
    [6] V. D’silva, S. Ramesh, and A. Sowmya, “Synchronous Protocol Automata: a framework for modeling and verification of SoC communication architecture,” in Proc. Design, Autom. Test Eur, pp.390-395, Feb. 2004.
    [7] R. Passerone, J. A. Rowson, and A. Sangiovanni-Vincentelli, “Automatic Synthesis of Interfaces between Incompatible Protocols,” in Proc. Eur. Conf. Design Automat., pp.8-13, Jun. 1998.
    [8] V. Androutsopoulos, D.M. Brookes, and T.J.W. Clarke, “Protocol Converter synthesis,” IET Comp. Digit. Tech., vol.1, pp.217-229, Nov. 2004.
    [9] Y.W. Yao, W.S. Chen, and M.T. Liu, “A Modular Approach to Constructing Protocol Converters*,” in Proc Int. Conf. Computer Communications, pp.572-579, Jun. 1990.
    [10] B. Park, H. Choi, and C. M. Kyung, “Synthesis and Optimization of Interface Hardware between IP’s Operating at Different Clock Frequencies,” in Proc. Int. Conf. Comput. Design, pp.519-524, Sept. 2000.
    [11] T. Chelcea and S.M. Nowak, "Robust interfaces for mixed-timing systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 8, pp. 857-873, Aug. 2004.
    [12] T. Cormen, C. Leiserson, and R. Rivest, Introduction to Algorithms, MIT press, Cambridge, MA, 2001.
    [13] A. Dasdan, S.S. Irani, and R.K. Gupta, “Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems ,” in Proc. Eur. Conf. Design Automat, pp.37-42, Jun. 1999.
    [14] C. E. Cummings, “Synthesis and Scripting Techniques for Designing Multi- Asynchronous Clock Designs,” Synopsys Users Group Conference, User Papers, March 2001, Section MC1, 3rd paper.
    [15] “AMBA Specification, Rev. 2.0,” May 1999
    [16] “AMBA AXI Protocol Specification,” Mar. 2004
    [17] “Open Core Protocol Specification, Rev. 2.2,” 2007
    [18] Synopsys—the Synthesis Company, DesignWare AHB Verification IP Databook, 2006.
    [19] “PrimeCell Infrastructure AMBA2 AHB to AMBA3 AXI Bridges, Rev. r0p1,” Feb. 2006.

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