近年來由於考量能源供應危機，因此如何節約能源及有效運用能源已愈趨重要。有鑑於此，本論文即研究提出以硬體實現經濟調度演算流程為系統核心，並採用積體電路之設計，期能經由場規劃邏輯閘陣列與嵌入式處理器之設計技巧，以有助於加速電力系統之經濟調度，其中並針對經濟調度演算法，提出相對應之演算架構及導入系統晶片設計，致力於經濟調度演算模組與嵌入式處理器之整合研製。而為證實本研究方法之可行性，並已執行模擬測試與時脈分析，測試結果應有助於佐證本研究方法對於協助減少發電成本所具有之發展潛力。

With an increasing concern on the energy crisis, the conservation and utilization of energy has become crucially important. In view of such importance, this thesis is aimed at the study on the hardware realization for the economic dispatch. In the proposed approach, the method employed the field programmable gate array as well as embedded processor in anticipation of increasing the computation performance. Meantime, the algorithmic structure and the system-on-a-chip were also applied such that the economic dispatch can be well realized with the aid of embedded processor. To validate the effectiveness of this method, simulations and analysis were both prudently made. Test results help confirm the potential of the proposed method for the generation cost reduction examined.

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