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研究生：	黃昱銓 Huang, Yu-Cheng
論文名稱：	用於音頻應用之低功耗縮放式類比數位轉換器 Low Power Zoom ADCs for Audio Applications
指導教授：	張順志 Chang, Soon-Jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2025
畢業學年度：	113
語文別：	英文
論文頁數：	158
中文關鍵詞：	縮放式類比數位轉換器、動態放大器
外文關鍵詞：	Zoom ADC, Dynamic Amplifier
相關次數：	點閱：14 下載：1
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本論文由兩個部分組成，第一部分實現了一個三階縮放式類比數位轉換器，使用動態放大器於第二級和第三級積分器降低功率消耗。使用台積電180奈米CMOS製程進行設計與驗證，當晶片操作在輸入電壓1.8伏特下，取樣頻率為每秒512萬次，頻寬為2萬赫茲 ; 在輸入訊號頻率為2千赫茲時，量測之訊號雜訊失真比達到102.8dB ; 晶片消耗652.5微瓦，換算得到整體效能指標是177.7dB。
第二部分提出一個使用視窗偵測技術應用於三階縮放式類比數位轉換器，動態偵測並調整參考電壓範圍，減少超取樣率以及三角積分類比數位轉換器中迴路濾波器的量化誤差訊號大小，降低整體功率消耗並提高訊號雜訊失真比。使用台積電180奈米CMOS製程進行設計與驗證，當晶片操作在輸入電壓1.65伏特下，取樣頻率為每秒340萬次，頻寬為2萬赫茲 ; 在輸入訊號頻率為1千赫茲時，量測之訊號雜訊失真比達到103dB ; 晶片消耗401微瓦，換算得到整體效能指標是180dB。

This thesis consists of two parts. The first part implements a third-order Zoom Analog-to-Digital Converter (ADC) utilizing dynamic amplifiers in the second and third integrators to reduce power consumption. Designed and verified using the TSMC 180-nm CMOS process, the chip operates at an input voltage of 1.8-V with a sampling rate of 5.12 MS/s and a bandwidth of 20 kHz. When processing an input signal at 2 kHz, the measured Signal-to-Noise-and-Distortion Ratio (SNDR) reaches 102.8 dB. The chip consumes 652.5 µW, achieving a Schreier Figure-of-Merit (FoMs) of 177.7 dB.
The second part proposes a window detection technique applied to a third-order Zoom ADC, which dynamically detects and adjusts the reference voltage range. This approach reduces OSR and the quantized error signal magnitude within the delta-sigma ADC loop filter, lowering overall power consumption while improving the SNDR. Also designed and verified using the TSMC 180-nm CMOS process, the chip operates at an input voltage of 1.65-V with a sampling rate of 3.4 MS/s and a bandwidth of 20 kHz. When processing an input signal at 1 kHz, the measured SNDR reaches 103 dB. The chip consumes 401 µW, achieving a Schreier Figure-of-Merit (FoMs) of 180 dB.

摘  要	I
Abstract	II
Table of Contents	III
List of Tables	VII
List of Figures	VIII
Chapter 1	Introduction	1
1	Background	1
2	Organization of the thesis	4
Chapter 2	Fundamentals of Analog-to-Digital Converter	5
1	Basic knowledge of ADC	5
1.1	Sampling	6
1.2	Quantization	8
1.3	Oversampling	10
1.4	ADC Metrics	12
1.4.1	Signal-to-Noise Ratio (SNR)	12
1.4.2	Signal-to-Noise and Distortion Ratio (SNDR)	13
1.4.3	Spurious-Free Dynamic Range (SFDR)	13
1.4.4	Effective Number of Bits (ENOB)	14
1.4.5	Dynamic Range (DR)	14
1.4.6	Total Harmonic Distortion (THD)	14
1.4.7	Effective Resolution Bandwidth (ERBW)	15
1.4.8	Figure-of-Merit (FoM)	16
2	Basic knowledge of Delta-Sigma Modulator	16
2.1	Noise-shaping	17
2.2	Loop Filter Topologies	20
2.2.1	Feedback type	21
2.2.2	Feedforward type	23
2.2.3	Multi-stage Delta Sigma Modulator (MASH)	25
2.2.4	Sturdy-MASH	27
2.2.5	Noise-Coupled	28
3	Delta-Sigma ADC Topologies	28
3.1	Discrete-time DSM	28
3.2	Continuous-time DSM	29
3.3	Single bit quantizer vs. multi-bit quantizer	31
3.4	Comparison of DTDSM and CTDSM	32
Chapter 3	Fundamental of Zoom ADC Architecture	33
1	Loop Filter Swing Issue	33
2	Zoom ADC Architecture	35
3	Successive Approximation Register (SAR) ADC	37
4	Error Sources of the System	39
4.1	Over-Ranging	39
4.2	Gain Error and STF	42
4.3	Maximum Input Frequency	43
4.4	DAC Mismatch and DEM	45
4.5	Finite Gain, Slew Rate and Bandwidth of OTA	46
4.6	Thermal Noise and OTA Input Referred Noise	48
4.6.1	Thermal Noise	48
4.6.2	OTA Input Referred Noise	49
Chapter 4	A 20kHz-BW Discrete-Time Dynamic Zoom ADC	52
1	Introduction	52
2	Design Goal and Analysis	52
3	Zoom ADC Circuit Design	58
3.1	Zoom ADC Noise Consideration	59
3.1.1	1st OTA Noise	60
3.1.2	Sampling Noise	61
3.1.3	DSM DAC Mismatch	61
3.1.4	DWA	62
3.2	OTA Design	64
3.2.1	OTA Gain, Bandwidth and Structure	64
3.2.2	Current-Starved OTAs	65
3.2.3	Floating Inverter Amplifier (FIA)	71
3.3	Bootstrapped Switch	72
3.4	CDAC Array	73
3.5	1-bit Quantizer	74
4	5-bit Coarse SAR ADC	76
4.1	Comparator	77
4.2	DAC	79
4.3	SAR Logic	81
5	Combinational Logic	83
6	Behavior Model, Chip Layout and Simulations	84
6.1	Behavior Model Results	84
6.2	Chip Layout	86
6.3	Simulation Results	87
7	Chip Micrograph, PCB and Measurement Results	90
7.1	Chip Micrograph and PCB Environment Setup	90
7.2	Measurement Results and Comparison Table	93
Chapter 5	A Dynamic Zoom ADC with Window Detect Reference Range	97
1	Introduction	97
2	Proposed Technique	97
3	Design Goal and Block Diagram	102
4	Circuit Description	104
4.1	The Proposed Window Detection Logic	104
4.2	Sampling Noise and CDAC Linearity	106
4.3	OTA	107
4.4	Bootstrapped Switch	108
4.5	1-bit Quantizer	109
4.6	SAR ADC	110
5	Behavior Model, Chip Layout and Simulations	111
5.1	Behavior Model Results	111
5.2	Chip Layout	116
5.3	Simulation Results	118
6	Chip Micrograph, PCB and Measurement Results	121
6.1	Chip Micrograph and PCB Environment Setup	121
6.2	Measurement Results and Comparison Table	124
6.3	Discussion	129
Chapter 6	Conclusion and Future Works	135
1	Conclusion	135
2	Future Works	136
Bibliography	137
                                    

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