本論文使用提出之線性化技術完成三顆高速高解析電流汲取式數位類比轉換器(DAC)晶片，分別為使用輸出阻抗補償(OIC)技術及同心平行四邊形繞線(CPR)技術完成之奈奎斯特歸零DAC晶片、使用切換突波補償(SGC)技術完成之奈奎斯特非歸零DAC晶片、及超奈奎斯特DAC晶片。分別說明如下：
為了實現低功耗、小面積和高速高解析的DAC，本論文提出了一種小尺寸非疊接電流單元。亦提出了一種使用補償電阻的輸出阻抗補償(OIC)技術，來補救由於非疊接電流單元輸出阻抗不足而引起的非線性，其中該補償電阻由一個碼相依閘極控制的PMOS實現。另外，提出的同心平行四邊形繞線(CPR)技術令每個電流單元的子單元被排列成具有共同質心的平行四邊形形狀，因此可減少不匹配誤差和電流單元間繞線引起的時間偏移。此外，在兩個相鄰信號之間插入零差動輸出的歸零(RZ)方法用來防止輸出變化受先前信號的影響。以28 nm CMOS製程實現的奈奎斯特歸零DAC晶片在10 GS/s的整個奈奎斯特頻帶上達到> 65 dBc的無雜散動態範圍(SFDR)和 < -70 dBc的三階互調失真(IM3)。在1.1 V單電源供電時，僅消耗162 mW。
對於未來的通信應用，在寬頻帶上具有高線性度的DAC已引起越來越多的關注；但是，切換突波會降低線性度。儘管RZ方法可以減少切換突波效應，但它會導致高達6 dB的信號功率損耗。本論文提出了切換突波補償(SGC)，它使用數位突波轉換器(DGC)來保持固定的切換次數，從而克服了非歸零(NRZ)的切換突波效應和碼相依的電源抖動問題。因此，可以在寬頻帶上實現高線性度而不會造成信號功率損失。一14位元10 GS/s奈奎斯特非歸零DAC晶片使用所提出之SGC於28nm CMOS製程中實現。量測結果顯示，在10 GS/s的整個奈奎斯特頻帶上，此DAC達到 > 64 dBc 的SFDR及< -77 dBc的IM3。與解析度 ≥ 10位元和取樣頻率 ≥ 6 GHz的其他最佳CMOS 奈奎斯特非歸零DAC相比，此奈奎斯特非歸零DAC晶片擁有最小面積為0.1 mm2、最低功耗為177 mW和最佳的性能指標(FoM)。
為符合奈奎斯特定理，奈奎斯特DAC的最高輸出信號頻率為取樣頻率的一半。近年，超奈奎斯特(over-Nyquist) DAC利用帶通濾波器於較高奈奎斯特區(Nyquist zones)將鏡像訊號(Image signal)提取出來當作DAC的輸出信號，所以超奈奎斯特DAC的輸出信號頻率可高於取樣頻率一半以上。本論文提出一可應用於超奈奎斯特DAC的切換突波補償技術(SGC)，並以28 nm CMOS製程實現，此超奈奎斯特DAC晶片可於10GS/s運作下支援0~10GHz訊號輸出。後模擬結果顯示，於輸出 0~10GHz訊號時，此DAC達到 > 61 dBc 的SFDR。與近年一流文獻相比，FoM為最佳。

In this dissertation, proposed linearization techniques are used to implement three high-speed high-resolution current-steering digital-to-analog converters (DACs), including a Nyquist return-to-zero (RZ) DAC with proposed output impedance compensation (OIC) and concentric parallelogram routing (CPR) techniques, a Nyquist non-RZ (NRZ) DAC with proposes switching-glitch compensation (SGC), and an over-Nyquist DAC with proposes SGC. The three DACs are described in the following.
To achieve a DAC with small area, low power consumption and high linearity over a wide bandwidth, small-size non-cascoded current cells is proposed. An OIC technique using a compensation resistor, implemented by a PMOS with code-dependent gate voltage control, is proposed to remedy the nonlinearity induced by the insufficient output impedance of the non-cascoded current cells. In addition, a proposed CPR technique, in which the sub-cells of each current cell are arranged such that they form a parallelogram shape with a common centroid, is used to reduce both the mismatch error and the routing-induced timing skew among the current cells. Furthermore, the RZ method, which inserts a zero differential output between two adjacent signals, is used to prevent output transition from the influence of the previous signal. The Nyquist RZ DAC, implemented in a 28-nm CMOS process, achieves > 65 dBc spurious-free dynamic range (SFDR) and < -70 dBc 3rd-order intermodulation distortion (IM3) over the entire Nyquist bandwidth at 10 GS/s while consuming 162 mW from a single 1.1 V supply.
For future communication applications, DACs with high linearity over a wide bandwidth have gained increasing attention; yet, the linearity is degraded by the switching glitch. Although the RZ method can reduce the switching-glitch effect, it causes up to 6dB signal power loss. This dissertation proposes SGC, which using a digital-to-glitch converter (DGC) to maintain a constant switching number, to overcome both the switching-glitch effect and code-dependent supply bouncing for NRZ DACs. Therefore, high linearity over a wide bandwidth is achieved without the signal power loss. Using the proposed SGC, a 14-bit 10GS/s Nyquist NRZ DAC is realized in 28nm CMOS. Measurement results show that the DAC achieves > 64 dBc SFDR and < -77 dBc IM3 over the entire Nyquist band at 10GS/s. Compared with other state-of-the-art CMOS Nyquist NRZ DACs with resolution ≥ 10bits and fs ≥ 6GHz, this DAC has the smallest area of 0.1mm2, the lowest power consumption of 177mW, and the best FoM performance.
To meet the Nyquist theorem, the highest available output signal frequency of Nyquist DAC is smaller than half sampling frequency. Recently, over-Nyquist DACs extracts the image signal in higher Nyquist zones by bnadpass filters as the output signal. Therefore, the available output signal frequency of over-Nyquist DAC can be larger than half sampling frequency. This dissertation modified the switching-glitch compensation (SGC) for over-Nyquist DAC in 28nm CMOS technology. Post-simulation results show this 10GS/s over-Nyquist DAC can synthesize output signal up to 10GHz and achieve > 61 dBc SFDR. Compared with other state-of-the-art CMOS DAC, this DAC has best FoM performance.

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