在本篇論文, 我們提出了連通管模型來解釋電荷重新分配這個物理現象, 根據此模型我們發展出能降低雜散電容對系統非線性影響的操作模式。而且, 我們也針對傳統的差動對逐漸趨近式類比數位轉換器,提出了一個改善的電路架構。我們針對兩個部分提出了最佳的設計方案。首先,為了避免在正負參考電壓的絕對值上的不匹配, 藉由不同的電容開關控制方式, 使用單獨參考電壓方法被提出。再者, 藉由移除解碼電路, 一個只需要一組暫存器的無多餘的逐漸近似暫存器更近一步的被簡化。
我們提出的方法可藉由軟體HSPICE的模擬結證明有效。我們的設計是採用台積電的0.25微米1P5M的製程。晶片面積(未加輸出入接腳)是大約 0.09 毫米平方, 且電源供應2.5V下消耗功率為2.27毫瓦特。 模擬結果顯示這個設計可以達到12bit 的解析度與50萬赫茲轉換速度。

In this thesis, we propose the immersed tube model (ITM) for charge distribution, and based on this mode we develop the operation method that diminishes nonlinearity from parasitical capacitor in the input terminal of the comparator. Then, we present a modified circuit architecture for the conventional fully differential SA (Successive-Approximation) A/D converter. The proposed method includes two optimal design solutions. First, in order to avoid mismatch in absolution of positive and negative reference voltages, a single reference voltage (SRV) method that removes the negative reference voltage is developed by the distinct switched capacitor controlling algorithm. Second, a non-redundant SAR, which needs only one set of registers, is farther simplified by removing the decode circuits.
These proposed methods are validated by the result of the simulation with HSPICE. This design adopted TSMC 0.25um 1P5M CMOS technology, and the core area is about 0.09 mm2. The simulation results show that this design can achieve 12-bit resolution and conversion rate 500kHZ. The core part draws 2.27 mW from a 2.5 power supply.

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