頻率合成器在無線通訊系統領域是相當重要的。由於現今的通訊系統規格不只一種，因此選用不同的規格對於輸出頻率的需求也會有所不同。本論文將選擇MB-OFDM超寬頻系統作為設計考量，針對其Group-1和Group-3的子頻帶的需求，總共有六個頻率輸出。
對於MB-OFDM超寬頻系統頻率合成器的頻率規劃不同會影響其電路面積與功耗，因此盡量減少子電路個數來達成設計目標是其重心。本論文製程部分使用台積電0.18-μm 1P6M CMOS 製程，其電路架構是由一個鎖相迴路為主，配合兩個多工器、兩個除頻器和兩個混頻器所組成。鎖相迴路部分的操作頻率為6336MHz，輸入參考頻率為264MHz，且為四相位輸出，故選用四相位壓控振盪器。在混頻器的部分主要是使用單側邊頻帶混頻器，設計兩種負載模式，其中利用電阻為負載的混頻器混頻出2640MHz，利用共振腔為負載的混頻出最後的7656MHz、7128MHz、6600MHz、4488MHz、3960MHz和3432MHz六個頻率。
整個頻率合成器系統的鎖相迴路對於其中的低通濾波器設計，使用的是二階迴路濾波器。在過去鎖相迴路的晶片實現大部分的濾波器都會使用外接的方式來完成，此方法可以降低晶片電路失敗的問題，但因為外接線與元件的影響，會產生各種額外的雜訊。因此本論文將對二階迴路濾波器做晶片的整合實現，除了可以降低雜訊的干擾，對於電荷幫浦的電流需求也較小，可降低其功率消耗。在電路架構上考量到頻率合成器的晶片面積，將使用電容放大技巧的二階迴路濾波器，除了可以減小實際使用電容的數值，也可以降低壓控振盪器控制電壓的抖動問題。
在晶片實現部分以鎖相迴路為主，電路架構由相頻偵測器、電荷幫浦、低通濾波器、壓控振盪器和四個除頻器所組成。主要電路包括壓控振盪器和兩個電流模式邏輯除二電路的電壓為1.5V，其他電壓則為1.8V。其中電荷幫浦使用rail-to-rail的放大器處理電流不匹配問題；低通濾波器使用電容放大的技巧來節省晶片的面積；且為了配合單側邊頻帶混頻器使用真實單相時脈四相位除三電路。整體的晶片面積為1.3 mm × 1.3 mm。在鎖定時四相位壓控振盪器的輸出功率為-7.63dBm，相位雜訊量測在100kHz位移頻率約為-86.07dBc/Hz、1 MHz位移頻率下約為-102.23dBc/Hz、10MHz位移頻率下約為-127.31dBc/Hz。其消耗功率為32mW，且輸入參考訊號所產生於壓控振盪器頻譜上的spur大小約為-49.4 dBm。
頻率合成器佈局後的功率消耗模擬結果可分為幾個部分：電阻為負載和共振腔為負載的兩個單側邊頻帶混頻器總消耗功率約為17.04mW，二選一和三選一的兩個多工器消耗功率約為6.92mW，整體之消耗功率為65.08mW，電壓使用1.5V。佈局的面積約為1.2 mm × 1.15 mm，此數據為核心電路部分將不包含PAD的面積。

The frequency synthesizer is an important role of the transceivers in the wireless communication systems. Today, various kinds of standard specifications are proposed for the communication systems. A different specification would lead to different frequency synthesizer's design. This thesis takes into account the frequency synthesizer design for the multi-band orthogonal-frequency-division-multiplexing (MB-OFDM) ultra-wideband (UWB) system, especially for the needs of Group-1 and the Group-3 sub-bands, in which there are six frequency outputs.
The different designs of frequency synthesizers will lead to different circuit area and power consumption. Therefore, how to reduce the complexity of the electric circuit integration while achieving the same function is the design key point. In this thesis, the frequency synthesizer was fabricated in TSMC’s 0.18m 1P6M CMOS process. Our proposed frequency synthesizer is composed of one phase-locked loop (PLL), two multiplexers, two dividers, and two single-sideband (SSB) mixers. The PLL is operated at 6336 MHz with a 264 MHz reference input. The PLL has to provides quadrature outputs for driving the SSB mixers, so a quadrature voltage-controlled oscillator (QVCO) is necessary. There are two types of output loads for the SSB mixers; one is a resistive type for the operation frequency 2640 MHz; another is an LC-resonant type for those operation frequencies are 7656, 7128, 6600, 4488, 3960, and 3432 MHz.
The PLL in the proposed UWB frequency synthesizer uses a second-order low pass filter (LPF). In the past, PLLs may utilize off-chip LPFs for the design flexibility consideration. This way can help to reduce the chip fail problem, but it will possibly cause more noises in the PLL. In this thesis, we use the on-chip LPF design that can have lower noise and less pump current level. Therefore, the power consumption of the charge pump circuit can be reduced. To consider the area consumption of the whole frequency synthesizer, the use with capacitive multiplication technique on the LPF can make the capacitor area small and the jitter performance of the QVCO improved. The capacitive multiplication technique is implemented with the help of an OP amplifier.
The primary contribution of this thesis is the integration of a PLL, which consists of a phase frequency detector, a charge pump, an on-chip low pass filter, a QVCO and four dividers. The charge pump is implemented by a rail-to-rail error amplifier to overcome the process variation and the current matching problem. The low pass filter use capacitive multiplication technique with a smaller capacitance value and thus the chip area can be reduced. Considering the cooperative use of the SSB mixers in our proposed frequency synthesizer, a novel quadrature TSPC divide-by-3 circuit has been proposed. The total chip area is 1.3 mm × 1.3 mm. The output power is -7.63 dBm. The measured average phase noises of the PLL is -86.07 dBc/Hz at 100kHz offset from the center frequency. That of -102.23 dBc/Hz and -127.31 dBc/Hz at 1 MHz and 10 MHz offset frequencies, respectively, from the center frequency can be obtained. The power consumption is 32mW and the reference spur is -49.4 dBm.
The post-layout simulation has been done for our proposed frequency synthesizer. The two SSB mixers respectively with an RC load and an LC load totally consumes the power consumption of 17.04 mW. The two multiplexers respectively with the bi-ways and tri-ways in power consumption are 6.92 mW. The total power consumption is 65.08mW and the vdd is 1.5V. The layout area is 1.2 mm × 1.15 mm without PAD.

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