目前在半導體晶圓製造過程中乃是使用控片來檢視機台製程能力與狀況。在進行控片測機時，則須暫停生產片之製造，如此所消耗的控片疊積成本與停機和換線以便進行檢視機台製程能力的時間消耗成本是相當可觀的。
本研究之目的為應用全自動虛擬量測(AVM)於半導體塗佈製程控片上，藉由收集生產片之製程資訊，來轉換成原採控片測機時所欲獲得的資訊結果；另外，再運用智慧型取樣決策機制，來減少控片測機的頻率，以有效地減少因執行控片量測所帶來的成本及生產週期時間(Cycle Time)損失。若能直接對控片測機執行次數縮減，將量測頻率減半執行，便可將原來用於控片測機所花費的時間，轉運用於生產產品，如此即可達成產能提升及降低生產成本之目標。

In today’s semiconductor fabrication process, the processing capability of the production machine is checked via monitoring wafers to ensure the quality of produced wafers. As such, the wafer production process should be terminated prior to wafer monitoring and this suspension for halting production to test monitoring wafers will result in a considerable wastes of time and cost.
Therefore, the purpose of this research is to apply the Automatic Virtual Metrology (AVM) technology to the coating process of monitoring wafers so that most of the processing capability of the production machine can also be conjectured from the process data collected of the production wafers. Then, by applying the Intelligent Sampling Decision (ISD) scheme, the sampling frequency of the monitoring wafers can be reduced effectively to reduce the waste of the cost and cycle time caused by the implementation of the monitoring wafers. If the quantity of the monitoring wafers can be directly reduced, such as measurement frequency lowered by half, the time spent on the monitoring wafers originally can then be shifted to wafer production. This can not only decrease the monitoring wafers used, but also provides machine utilization. In this way, the goals of production capacity enhancement and production cost reduction can be achieved.

[1] Hong Xiao (2014). Introduction to Semiconductor Manufacturing Technology 2/E .Taipei:Quanhua .
[2] F.-T. Cheng, J. Y.-C. Chang, H.-C. Huang, C.-A. Kao, Y.-L. Chen, and J.-L. Peng," Benefit Model of Virtual Metrology and Integrating AVM into MES,“ IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 2, pp. 261-272, May 2011.
[3] F.-T. Cheng, H.-C. Huang, C.-A. Kao, "Developing an automatic virtual metrology system", IEEE Transactions on Automation Science and Engineering., vol. 9, no. 1, pp. 181-188, Jan. 2012.
[4] F.-T. Cheng, H.-C. Huang, and C.-A. Kao, “Dual-Phase Virtual Metrology Scheme”, IEEE Transactions on Semiconductor Manufacturing, vol. 20, no. 4, pp. 566-571, November 2007.
[5] M.-H. Hung, T.-H. Lin, F.-T. Cheng, R.-C. Lin, “A novel virtual metrology scheme for predicting CVD thickness in semiconductor manufacturing”, IEEE/ASME Transactions on mechatronics, vol. 12, no. 3, pp. 308-316, June 2007.
[6] C. Chen, F. Cheng, C. Wu and H. Huang, "Preliminary study of an intelligent sampling decision scheme for the AVM system," 2014 IEEE International Conference on Robotics and Automation (ICRA), Hong Kong, 2014, pp. 3496-3501.
[7] B. Foster, D. Meyersdorf, J. M. Padillo and R. Brenner, "Simulation of test wafer consumption in a semiconductor facility," IEEE/SEMI 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (Cat. No.98CH36168), Boston, MA, USA, 1998, pp. 298-302.
[8] Chung, S. H. and Yang, Y. S. A scenario-based stochastic programming model for the control or dummy wafers downgrading problem. Appl. Stoch. Model. Bus. Ind. 2009. 25: 263–274.
[9] E. C. Ozelkan and M. Cakanyildirim, "Test wafer management for semiconductor manufacturing," in IEEE Transactions on Semiconductor Manufacturing, vol. 19, no. 2, pp. 241-251, May 2006.
[10] A. Faruqi, R. Goss, D. Adhikari and T. Kowtsch, "Test Wafer Management and Automated Wafer Sorting," 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Cambridge, MA, 2008, pp. 322-326.
[11] Chuen-Shiuan Liou, T. K. Lin, B. Tu and A. Chang, "Capacity forecast model for control and dummy wafers," ISSM 2005, IEEE International Symposium on Semiconductor Manufacturing, 2005., San Jose, CA, 2005, pp. 123-125.
[12] W. K. Ho, A. Tay, M. Chen, J. Fu, H. Lu and X. Shan, "Critical Dimension Uniformity Via Real-Time Photoresist Thickness Control," in IEEE Transactions on Semiconductor Manufacturing, vol. 20, no. 4, pp. 376-380, Nov. 2007.
[13] V. M. MARTINEZ and T. F. EDGAR, "Control of lithography in semiconductor manufacturing," in IEEE Control Systems Magazine, vol. 26, no. 6, pp. 46-55, Dec. 2006.
[14] Lay Lay Lee, C. D. Schaper and Weng Khuen Ho, "Real-time predictive control of photoresist film thickness uniformity," in IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 1, pp. 51-59, Feb. 2002.
[15] H. Y. Kang, A. H. I. Lee, "Critical dimension control in photolithography based on the yield by a simulation program", Microelectron. Reliab., vol. 46, no. 56, pp. 1006-1012, 2006.
[16] Postnikov, S., et al. "Critical dimension control in optical lithography." Microelectronic Engineering 69.2-4 (2003): 452-458.