本篇論文提出一個新穎的遞迴離散傅立葉轉換，並整合了質數因子與公因數因子的傅立葉轉換演算技巧。此外，離散傅立葉轉換可被延伸用於計算修正型離散正、逆轉換於音訊編解碼標準中。對於數位廣播(DRM)接收器的音訊解碼器而言，離散傅立葉轉換處理器用於正交頻率分時多工(OFDM)技術中，可與先進音訊編碼技術(AAC)之解碼器節省並共享其硬體資源。
過去文獻中所提出之遞迴架構解決方案往往受限於計算的速度過慢，造成晶片功率消耗過高。而平行架構之設計方式在設計可變長度的DFT運算不夠彈性且需要大量的處理單元，造成晶片面積過大。因此，本篇論文擷取兩種架構之優點，遂提出一個高速計算、高功率效益、及可參數化的遞迴式離散傅立葉設計方案，所提出之技術可總結如下: (1) 利用硬體資源共享與re-timing等技巧來達成一個精簡的RDFT處理核心設計；(2) 避免正弦與餘弦係數隨著不同的轉換長度地增長，提出免查表式係數產生器；(3) 結合質因數、公因數演算法將一個N點的DFT運算縮減為c點與m點的子DFT運算，降低計算複雜度與計算週期。如此，一個新穎的遞迴離散傅立葉轉換(質因數演算法+公因數演算法+遞迴離散傅立葉轉換)將可大大的減少於可攜式DRM接收器的平台上的DFT與IMDCT晶片硬體實現成本。
本論文所提出的設計具有較高的資料吞吐率(DTPT)。就256點長度的DFT運算，若與最新的Lai等人的架構相較，我們提出的方法可有效地減少83%的乘法運算、86%的加法運算以及80%的計算週期。就1920點長度的IMDCT運算；若與最新的Li等人的演算法相較，我們提出的方法能大幅地地減少85%的乘法運算、81%的加法運算以及88%的計算週期。最後，我們採用台積電0.18um的製程技術來實現提出之處理器，設計之晶片的核心面積為840×840 um2，其功率消耗在25MHz的操作頻率下為14.6mW。結果顯示，相較於現有相關技術，本論文所提出之方法與架構將更有效與合適於DRM的應用。

This dissertation presents a novel recursive discrete Fourier transform (RDFT) integrated with the prime factor and common factor algorithms. The DFT algorithm is extended to compute the modified discrete cosine transform (MDCT) and it inverse transform (IMDCT) in audio codecs. For audio decoder in digital radio mondiale (DRM) receiver, the DFT processor in OFDM can share the hardware resources to the AAC decoder.
In previous approaches, the recursive architecture designs are often restricted to the slower computational speed, and it causes that the implemented chip consumes much higher power. On the other hand, the parallel architecture designs require more processing units and it is not a flexible design for variable transform lengths. Also, the chip size would become larger than recursive designs. Here, this dissertation proposes a fast-computational, power-efficient, and parametric RDFT design. It can be summarized as follows: (1) By using the hardware-sharing and re-timing schemes, we can implement a compact RDFT kernel design; (2) To avoid the growth of cosine and sine coefficients with different transform lengths, a look-up-table-free (LUTF) design is proposed to generate the coefficients; (3) Combining with prime factor (PF) and common factor (CF) algorithms to compute N-point DFT computations. The N-point DFT can be decomposed into c- and m-point sub-DFTs, and the computational complexity and cycle will be reduced. Hence, a high-performance RDFT algorithm (PFA + CFA + RDFT + LUTF) is proposed, and it would greatly reduce the hardware costs in implementation of DFT and IMDCT on a platform of portable DRM receiver.
The proposed design has higher data throughput per transformation (DTPT) than other existing DFT and IMDCT processors. For 256-point DFT computations, the proposed method can significantly reduce 83% of multiplications, 86% of additions, 80% of computational cycles compared with recent Lai et al.’s RDFT. For 1920-point IMDCT computations, the proposed method can significantly reduce 85% of multiplications, 81% of additions, 88% of computational cycles compared with recent Li et al.’s IMDCT. Finally, we also realize the proposed RDFT processor by using TMSC 0.18um 1P6M CMOS technology. The core size is 840×840 um2 and the power consumption is 14.6mW @ 25MHz. The results show that it would be more efficient and more suitable than previous works for DRM applications.

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