本論文為設計應用於雙頻無線通訊系統之射頻前端子電路設計，內容可分為兩個部分：第一部分為5.5 GHz變壓器回授低雜訊放大器，第二部分為2.4 GHz次諧波注入鎖定鎖相迴路。在本論文中兩個電路皆採用TSMC 0.18 μm CMOS製程實現，並且以fully-on-wafer的方式進行量測。
在5.5 GHz變壓器回授低雜訊放大器電路中，本設計透過變壓器回授共源極架構，利用變壓器耦合作為核心回授路徑，藉由其獨特的電抗回授特性，成功在不引入額外熱雜訊的情況下實現寬頻輸入阻抗匹配，進而有效降低傳統匹配網路所帶來的雜訊貢獻，同時兼顧高增益與低雜訊性能。此外，該變壓器元件亦能同時達成阻抗轉換與電感整合之功效，顯著有助於降低晶片核心面積。相較於傳統電阻回授或共閘極架構，本設計於頻寬、雜訊指數、設計彈性上皆具備較佳之整體表現。在電路設計上，透過調整變壓器匝數比與電晶體轉導，可有效控制輸入導納之實部與虛部，進一步提升匹配能力與整體效能表現。量測結果顯示，在5 - 6 GHz頻段內，輸入與輸出反射係數皆小於 -10 dB，在5.5 GHz時最大功率增益為19.74 dB，最低雜訊指數為2.9 dB，輸入三階截斷點(IIP₃)為 −16.5 dBm，一分貝增益壓縮點(P1dB)為 −26 dBm，整體功率消耗為5.32 mW。
在2.4GHz次諧波注入鎖定鎖相迴路電路中，本設計首先將參考訊號經由壓控延遲線(VCDL)調整其延遲時間，再透過脈波產生器(PG)產生具備適當脈波寬度之注入訊號，並將其週期性地注入至壓控振盪器中。相較於傳統整數型鎖相迴路，SIL-PLL藉由參考時脈的週期性脈衝注入，迫使振盪器進行相位重對準(phase realignment)，從而有效消除壓控振盪器內部隨時間累積之相位抖動；此機制不僅能顯著降低迴路內(in-band)雜訊，亦可部分抑制迴路外(Out-of-band)雜訊，進一步放寬對壓控振盪器本身的雜訊性能要求。在本電路量測中，參考頻率輸入為150 MHz，輸出頻率為2.4 GHz，相較於未開啟注入機制之傳統PLL，當SIL-PLL開始運作時，於在頻率偏移量為1 MHz時的相位雜訊由 -108.8 dBc/Hz大幅改善至 -117.64 dBc/Hz，雜訊性能顯著提升約9 dB。同時，其積分均方根時脈抖動量亦由853 fs有效降低至671 fs(1 kHz–30 MHz)，此時參考突波強度約為 -42.8 dBm，輸出功率為 -3.62 dBm，核心電路之功耗為7.36 mW。

This thesis presents the design and implementation of radio frequency (RF) front-end sub-circuits for dual-band wireless communication systems. The research is divided into two parts: a 5.5 GHz Transformer Feedback Low Noise Amplifier (LNA) and a 2.4 GHz Sub-Harmonic Injection-Locked Phase-Locked Loop (SIL-PLL). Both circuits were implemented using the TSMC 0.18 μm CMOS process and characterized via fully-on-wafer measurements.
In the 5.5-GHz transformer-feedback LNA design, a transformer-coupled common-source topology is adopted as the core feedback path. By leveraging its reactive feedback characteristics, wideband input impedance matching is achieved without introducing additional thermal noise, thereby reducing the noise contribution of conventional matching networks while maintaining a balance between gain and noise performance. Moreover, the transformer simultaneously performs impedance transformation and inductor integration, effectively reducing chip area. Compared to conventional architectures, the proposed design achieves improved performance in bandwidth, noise figure, and design flexibility. The input admittance is optimized through transformer turns ratio and transistor transconductance (gm), enhancing matching performance.
Measurement results demonstrate that within the 5 – 6 GHz target band, both the input (S11) and output (S22) reflection coefficients remain well below -10 dB. At the target operating frequency of 5.5 GHz, the LNA achieves a maximum power gain of 19.74 dB, a minimum noise figure (NF) of 2.9 dB, an input third-order intercept point (IIP3) of -16.5 dBm, and a 1-dB gain compression point (P1dB) of -26 dBm. Concurrently, the circuit satisfies the unconditional stability criteria across the entire frequency range, with a total power consumption of only 5.32 mW.
For the second part, a 2.4-GHz SIL-PLL is proposed to enhance spectrum purity. The reference clock is processed by a voltage-controlled delay line (VCDL) and a pulse generator (PG) to produce periodic injection pulses for the VCO. This technique enforces phase realignment and suppresses accumulated phase jitter, effectively reducing both in-band and out-of-band noise.
Measurement results indicate that under a 150-MHz reference and a 2.4-GHz output, the phase noise at 1-MHz offset improves from -108.8 dBc/Hz to -117.64 dBc/Hz, achieving about a 9 dB reduction. The RMS jitter is reduced from 853 fs to 671 fs (1 kHz to 30 MHz). The measured reference spur is -42.8 dBm, output power is -3.62 dBm, and core power consumption is 7.36 mW.

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