隨著進入SoC的時代，系統內部不在只是單一個功能，而是有多個元件所組成的應用架構。從高階演算法層級到低階的邏輯閘設計上，所要考慮的因素很多，例如匯流排的設定、Block的配置、如何做到HW/SW同時模擬…，導致在設計時間上跟複雜度變的相當高，讓設計者必須考慮的因素變的很多。如果有個設計流程自動化的流程幫助設計者，讓設計者能夠快速模擬跟驗證也就變成越來越重要。

在本論文中提出一個可將CDFG從Behavior Level的描述轉譯Transaction Level的SystemC，內部含有跟匯流排溝通的介面，在透過我們建立以匯流排為基礎的虛擬平台上，讓設計者有個初步的系統架構，最後能透過我們的平台，做快速的驗證跟模擬，加速設計上的流程。

Upon entering SoC era, an IC chip contains more functionalities than ever before. For a top-down system design, it is required to design from higher levels of design abstraction (like algorithm or behavior level) down to gate level. However, there are abundant of considerations to be considered when transforming the design from the behavior level to hardware implementation, including the setting of bus configurations, block allocations, HW/SW co-simulation and so on. The complexity of this transformation has incurred quite an amount of design effort and consumes a long period of time. An automatic design tool that can help designers to simplify the design flow while providing fast simulation and verification is of great importance.

In this thesis, an automatic design tool that can translate the CDFG format from behavior level to transaction level SystemC is proposed. A bus communication interface is incorporated inside the tool to allow designers to use the generated bus-based platform for system evaluation. The tool also provides a basis for verification to carry out fast simulation and verification so that the design time could be greatly shortened.

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