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研究生： 許哲維
Hsu, Che-Wei
論文名稱： 一個基於上板殘值增益校正之八位元每秒取樣十六億次快閃輔助逐漸趨近時間交錯式類比數位轉換器
A 1.6-GS/s 8-bit Flash Assisted SAR Time-Interleaved Analog-to-Digital Converter with Top-plate Residue Based Gain Calibration
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 122
中文關鍵詞： 類比數位轉換器 、快閃輔助逐漸趨近式 、時間交錯式 、增益校正
外文關鍵詞： analog-to-digital converter, Flash-SAR, time-interleaved, gain calibration
相關次數： 點閱：196  下載：66 
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    • 本論文提出一個四通道8位元每秒取樣十六億次的快閃輔助逐漸趨近時間交錯式類比數位轉換器。本設計採用了結合快閃與逐漸趨近式的複合式架構，得利於快閃操作，單通道的取樣速度可提升至每秒4千萬次。此多通道類比數位轉換器將多種不匹配效應都納入設計考量，包含補偏、增益以及時序偏移等不匹配。此設計使用改良後的拔靴式取樣電路來抑制時序偏移；並且加入了簡單的電路來實現類比式背景補偏校正；同時提出了全新的增益校正技巧，藉由在逐漸趨近式類比數位轉換器中創造出和增益單調正相關的訊號，並基於此訊號來判斷增益不匹配，其只需簡單地控制電容陣列便可完成增益補償，面積以及功耗負擔極小。
    本設計以台積電40奈米CMOS製程進行晶片下線驗證，晶片面積為0.29mm2。當晶片操作在輸入電壓1伏特與取樣速度十六億次時消耗功率為16.76mW，測試結果顯示在低輸入頻率下校正開啟前後訊號雜訊失真比/有效位元能從34.59 dB /5.45位元上升到44.15-dB /7.04 位元，換算得到的轉換效率為78.93 fJ/conversion-step。而在奈奎斯特(Nyquist-rate)輸入頻率下，可以達到38.32 dB的訊號雜訊失真比，換算得到的轉換效率為155.9 fJ/conversion-step。

    This thesis presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC (TI-ADC). The architecture in each channel is a hybrid combination of flash ADC for enhancing the operating speed and successive-approximation register ADC for saving the power consumption. Channel mismatches including offset, gain and timing-skew mismatches have been taken into consideration in designing the 4-channel TI-ADC. A modified bootstrap circuit is used to inhibit timing-skew mismatch. A background analog calibration scheme without inducing complicated circuitries is employed to solve the offset mismatch. A background gain calibration method is proposed to reduce gain mismatch in this work. This proposed method detects a common-mode voltage signal correlated with gain error of a SAR ADC and correct gain mismatch by simple calibration capacitor array, which costs only a little power and area overhead.
    A proof-of-concept chip prototype was designed and fabricated in TSMC 40-nm technology. The chip area is 0.29mm2. At 1.6 GS/s, the ADC consumes 16.76mW from a 1-V supply. Measurement results show the proposed gain-mismatch calibration is able to enhance SNDR from 34.59 dB to 44.15 dB , which leads to a FoM of 78.93 fJ/conversion-step. At Nyquist input frequency, the SNDR is 38.32 dB resulting a FoM of 155.9 fJ/conversion-step.

    摘 要 III Abstract IV List of Tables X List of Figures XI Chapter 1 Introduction 1 1.1 Background 1 1.2 Hybrid Architecture 4 1.3 Time-Interleaved ADCs 5 1.4 Organization 7 Chapter 2 SAR ADC 8 2.1 Introduction of SAR ADC 9 2.2 Speed analysis 11 2.2.1 Comparison Time 13 2.2.2 Comparator Reset Time 16 2.2.3 DAC Settling Time 17 2.2.4 Logic Delay 19 2.3 Techniques of Speed Enhancement 20 2.3.1 Loop-unrolled Technique 20 2.3.2 Redundancy Algorithm 22 2.3.3 Control Logic Design 30 2.4 Hybrid Architecture 32 2.4.1 Pipeline-SAR ADC 32 2.4.2 Sub-ranging SAR ADC 34 2.4.3 Flash-SAR ADC 36 Chapter 3 Time-interleaved ADC 38 3.1 Introduction of Time-interleaved ADCs 39 3.1.1 Single Channel Sampling 39 3.1.2 Time-Interleaved Sampling 42 3.2 Mismatch of TI-ADCs 47 3.2.1 Offset Mismatch 48 3.2.2 Gain Mismatch 50 3.2.3 Timing-skew 53 3.3 Calibration For TI Mismatch 56 3.3.1 Offset Calibration 57 3.3.2 Gain Calibration 59 3.3.3 Timing-skew Calibration 63 Chapter 4 A 1.6-GS/s 8b Time-Interleaved Flash-SAR ADC with Top-Plate Residue Based Gain Calibration 68 4.1 Introduction 68 4.2 Architecture And Design Consideration 70 4.2.1 Flash Assisted Time-Interleaved SAR 70 4.2.2 Redundancy Algorithm 72 4.2.3 DAC Switching Method 75 4.3 Techniques For Channel Mismatch 77 4.3.1 Low-skew Bootstrapped switch 77 4.3.2 Background Offset Calibration 79 4.3.3 Proposed Background Gain Calibration 81 4.4 Key Circuit Building Block 85 4.4.1 Bootstrapped Switch 85 4.4.2 Dynamic Comparators 87 4.4.3 Digital Control Logic Circuits 89 4.4.4 Clock Generator 92 4.4.5 Capacitive DAC 93 Chapter 5 Simulation and Measurement Results 95 5.1 Layout and Chip Floor Plan 95 5.2 Simulation Results 98 5.3 Die Micrograph and Measurement Setup 101 5.4 Measurement Results 105 Chapter 6 Conclusion and Future Works 113 Bibliography 116

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