簡易檢索 / 詳目顯示

回結果列表
研究生： 林友中
Lin, You-Chung
論文名稱： 離散餘弦轉換電路的設計與測試
Design and Test of Discrete Cosine Transform Circuits
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2003
畢業學年度： 91
語文別： 英文
論文頁數： 48
中文關鍵詞： 離散餘弦轉換
外文關鍵詞： discrete cosine transform
相關次數： 點閱：29  下載：3 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 我們描述了三個具有高錯誤涵蓋率和短測試時間的可測性二維離散餘弦轉換電路(DCT)。這三個二維離散餘弦轉換電路分別以行列分解法、直接法、折疊直接法被實現出來。在設計這些電路時，我們對這些電路作了一些修正以改善它們的錯誤涵蓋率。這些修正包括了掃描式設計、特殊設計和管線式設計，是依這些離散餘弦轉換電路的不同情況使用不同的修正。在對這些電路作修正後，它們的錯誤涵蓋率可以到達100%或接近100%。然而，在加入掃描式設計和管線式設計後，測試時間會被大幅的提高。因此我們使用了兩種叫作輸入腳位減少測試法和廣播掃描式測試法的測試方法去解決這個缺點。透過這兩種測試法，和加入掃描設計後的原始電路比較，測試時間可被降為原來的0.647% ~ 15.48%；且其所需增加的面積僅為原始電路面積的5.84% ~ 9.16% 。

    We present three testable 2-D Discrete Cosine Transform (DCT) circuits with high fault coverage and short test application time. The three DCT circuits are implemented with the row-column decomposition method, the direct method, and the folded direct method, respectively. We do some modifications when designing these DCT circuits to improve their fault coverage. These modifications include scan design, ad hoc design, and pipeline design, which are used according to different circumstances of these DCT circuits. After the modifications on these circuits, their fault coverage can reach 100% or near 100%. However, inserting scan design and pipeline design into the circuits would substantially increase the test application time. To overcome this defect, we apply two testing methods, namely the input reduction testing method and the broadcasting scan method, to these circuits. With these methods the test application time can be reduced to 0.647%~15.48% of those of the original circuits with single full scan design, and the area overhead is 5.84%~9.16% of those of the original circuits.

    CHAPTER1 INTRODUCTION 1 1.1. INTRODUCTION OF DCT 1 1.2. MOTIVATION AND TEST PLAN 2 1.3. ORGANIZATION OF THESIS 2 CHAPTER2 BACKGROUND AND PREVIOUS WORK 4 2.1. BACKGROUND IN DESIGN 4 2.1.1. Structures of the Row-Column Decomposition Method 5 2.1.2. Structure of the Direct Method 7 2.1.3. Structure of the Folded direct Method 10 2.1.4. Comparison of the Three Methods 12 2.2. BACKGROUND IN TESTING 12 2.2.1. Scan Design 13 2.2.2. Broadcasting Scan Testing Method 14 2.2.3. Input Reduction Testing Method 16 2.3. PREVIOUS WORK 18 2.3.1. DFT Approach Based on the M-testability Conditions 18 2.3.2. BIST on 2-D DCT 19 CHAPTER3 TEST STRATEGY AND TESTABLE DESIGN OF DCT CIRCUITS 20 3.1. TESTABLE DCT CIRCUIT OF THE ROW-COLUMN DECOMPOSITION METHOD 21 3.1.1. Testing Results of Original Circuit 21 3.1.2. Ad Hoc Design for Redundancy Elimination 22 3.1.3. Test Application Time Reduction 26 3.2. TESTABLE DCT CIRCUIT OF THE DIRECT METHOD 28 3.2.1. Testing Result of Original Circuit 29 3.2.2. Pipeline and Ad Hoc Design 29 3.2.3. Test Application Time Reduction 33 3.3. TESTABLE DCT CIRCUIT OF THE FOLDED DIRECT METHOD 34 3.3.1. Testing Result of Original Circuit 34 3.3.2. Ad Hoc Design for Redundancy Elimination 36 3.3.3. Pipeline Design 37 3.3.4. Test Application Time Reduction 39 CHAPTER4 EXPERIMENTAL RESULTS & COMPARISON 41 4.1. COMPARISON OF THE EXPERIMENTAL RESULTS OF THE 8*8 2-D DCT CIRCUIT OF THE ROW-COLUMN DECOMPOSITION METHOD 41 4.2. COMPARISON OF THE EXPERIMENTAL RESULTS OF THE 8*8 2-D DCT CIRCUIT OF THE DIRECT METHOD 42 4.3. COMPARISON OF THE EXPERIMENTAL RESULTS OF THE 8*8 2-D DCT CIRCUIT OF THE FOLDED DIRECT METHOD 43 CHAPTER5 CONCLUSIONS AND FUTURE WORK 45 5.1. CONCLUSIONS 45 5.2. FUTURE WORK 46 REFERENCES 47

    [1] ISO/IEC JTC1/SC29/WG10, JPEG Committee Draft CD10918, 1991.

    [2] ISO/IEC JTC1/SC29/WG11, MPEG Committee Draft CD11172, 1991.

    [3] CCITT Recommendation H.261, 1990 (Annex 1).

    [4] S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, H. Yerane, and M. Yoshimoto, “A 100 MHz 2-D Discrete Cosine Transform Core Processor,” IEEE J. Solid-State Circuit, vol. 27, pp. 492-499, Apr. 1992.

    [5] D. Slawecki and W. Li, “DCT/IDCT processor design for high data rate image coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 2, pp. 135-146, June 1992.

    [6] A. Madisetti and A. N. Willson, “A 100 MHz 2-D 8 8 DCT/IDCT Processor for HDTV applications,” IEEE Trans. Circuits Syst. Video Technol., vol 5, pp. 158-165, Apr. 1995.

    [7] H. Y. Lu, “A New Architecture and Its Implementation of a Discrete Cosine Transformer,” Master Thesis, Dept. of E.E., NCKU, Taiwan, June 1997.

    [8] P. Duhamel and C. Guillemot, “Polynomial Transform Computation of 2-D DCT,” in Proc. ICASSP’90, pp. 1515-1518, Apr. 1990.

    [9] N. I. Cho and S. U. Lee, “Fast Algorithm and Implementation of 2-D Discrete Cosine Transform,” IEEE Trans. Circuits Syst., vol. 38, pp. 297-305, Mar. 1991.

    [10] N. I. Cho, I. Y. Dong, and S. U. Lee, “On The Regular Structure for The Fast 2-D DCT Algorithm,” IEEE Trans. Circuits Syst., vol. 40, pp. 259-266, Apr. 1993.

    [11] Y. P. Lee, T. H. Chen, L. G. Chen, M. J. Chen, and C. W. Ku, “A Cost-Effective Architecture for 8 8 2-D DCT/IDCT Using Direct Method,” IEEE Trans. Circuits Syst. Video Technol., vol.7, pp. 459-467, June 1997.

    [12] J. H. Hsiao, L. G. Chen, T. D. Chiueh, and C. T. Chen, “High Throughput CORDIC-based Systolic Array Design for The Discrete Cosine Transform,” IEEE Trans. Circuits Syst. Video Technol., vol. 5, pp. 218-224, June 1995.

    [13] K. J. Lee, J. J. Chen, C. H. Huang, “Broadcasting Test Patterns to Multiple Circuits,” IEEE Trans. on CAD, pp. 1793~1802, 1999.

    [14] C. A. Chen and S. K. Gupta, “Efficient BIST TPG Design and Test Set Compaction via Input Reduction,” IEEE Trans. On CAD, vol. 17, pp. 692~705, Aug. 1998.

    [15] S. K. Lu, C. W. Wu, and S. Y. Kuo, “Design of Easily Testable VLSI Arrays for Discrete Cosine Transform,” Signals, Systems, and Computers Conference, vol. 2, pp. 989~993, Oct. 1992.

    [16] H. B. Kim, and D. S. Ha, “Design And Synthesis of Built-in Self-Testable Two-Dimensional Discrete Cosine Transform Circuits,” ASIC/SOC Conference, pp. 3~7, 2000.

    下載圖示 校內：2004-07-04公開
    校外：2004-07-04公開
    QR CODE