| 研究生: |
徐元平 Hsu, Yuan-Ping |
|---|---|
| 論文名稱: |
應用於調頻廣播前端接收器之88-108-MHz頻率合成器 A 88-108-MHz Frequency Synthesizer for FM Broadcast Receiver Front-end |
| 指導教授: |
郭泰豪
Kuo, Tai-Haur |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2004 |
| 畢業學年度: | 92 |
| 語文別: | 英文 |
| 論文頁數: | 82 |
| 中文關鍵詞: | 頻率合成器 、調頻廣播 |
| 外文關鍵詞: | 88-108-MHz, FM broadcast, Frequency Synthesizer |
| 相關次數: | 點閱:72 下載:3 |
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本篇論文提出一個應用於調頻前端接收器的互補金氧半頻率合成器。台灣目前所使用的調頻廣播系統頻帶為88.1MHz~107.9MHz,每個頻道寬度為200kHz,共有100個頻道可供選擇。因為混波器輸出頻率規格為225kHz,提供給後端帶通濾波器使用,故頻率合成器的輸出頻率為88.325MHz~108.125MHz;本次設計的電路輸出頻率範圍為87.725MHz~108.125MHz。
針對上述規格,此頻率合成器基於鎖相迴路的架構,採用輸入頻率為6.5MHz,內部電路包含有:三態相位頻率偵測器;充電器與迴路濾波器;此電路操作在100MHz左右的低頻範圍,若使用製程提供的被動電感實現震盪器,則有極大面積以及Q值較差的缺點,故採用主動電感式電壓控振盪電路來取代被動電感,可以大幅縮小面積與功率消耗,但主動電感的相位雜訊高於被動電感;四相位產生器可從壓控振盪電路的輸出再產生四個相差90∘相位的輸出頻率傳送給混波器;基於較低的輸入頻率,我們採用小數除頻器增加迴路頻寬來縮短鎖定的時間。
所設計的頻率合成器是實現於0.18μm 1P6M互補金氧半製程,主動面積為0.35x0.37mm。功率消耗為43.5mW。
This thesis presents a CMOS 88~108-MHz frequency synthesizer for FM receiver front-end. The frequency band of FM broadcast system in Taiwan is at 88.1MHz ~ 107.9MHz. There are 100 channels for choosing and channel spacing is 200kHz. Because the specification of mixer output frequency is 225kHz which is for bandpass filter, the output frequency range of frequency synthesizer is 88.325MHz ~ 108.125MHz. In this design, the output frequency range of the circuit is 87.725MHz ~ 108.125MHz.
For the specification described above, the input reference frequency of the frequency synthesizer based on Phase-Locked Loop (PLL) is 6.5MHz. The circuit contains several components: Tri-state Phase/Frequency Detector (PFD); Charge-pump and Loop-filter; The circuit operates at the low frequency about 100MHz, there will be some drawbacks that chip area is very large and low Q factor of oscillation if we use the process passive inductor for realizing oscillator. Therefore, we replace the passive inductor by an active inductor for voltage-controlled oscillator (VCO). The goal of small chip area and low power consumption can be approached. But the phase noise of active inductor is higher than passive inductor; Four-phase Generator from VCO to mixer will generate four phases each difference is 90∘; We use Fractional-N Divider in this designation in order to satisfy the lower input frequency and shorten lock time by increasing the loop bandwidth.
We design the frequency synthesizer in CMOS 0.18μm 1P6M process. Active area is 0.35x0.37mm. Power consumption is 43.5mW.
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