無論在超大型積體電路或半導體記憶體當中，可測試性設計對於硬體的品質與可靠度提升，一直扮演非常重要的角色。在各種可測試性設計方法當中，內建自我測試電路一直是不可或缺的方法之一。藉由在超大型積體電路及半導體記憶體中內建自我測試電路，我們可以減少晶片的輸入與輸出腳位，亦即能夠降低晶片面積與成本。除此之外，傳統透過測試機台傳送測試向量的方法，會受到測試機台延遲、測試載板延遲、晶片輸入輸出腳位延遲、連接線延遲的影響，使得測試用的時脈週期無法達到晶片實際運作的速度。透過內建自我測試電路，我們可以在晶片內部產生測試向量，並直接傳送到待測電路上進行測試，因此能夠提供實速測試。傳統的內建自我測試電路架構大致上可區分為針對數位邏輯電路架構以及針對半導體記憶體架構兩大類。近年來，新興非揮發性記憶體元件—憶阻器—被認為適合實現脈衝神經網路中的突觸運算。憶阻器除了能儲存神經網路權重，同時可以實現權重的乘加運算。此種以憶阻器建構之脈衝神經網路運算架構被認為能夠大幅提升神經網路運算的能源效率。為了提升其品質與可靠度，相關的硬體錯誤模型（慢積分錯誤與快積分錯誤）與測試演算法（SNN-Test）過去也已被提出。在這篇論文中，我們提出一個針對以憶阻器建構之脈衝神經網路硬體的內建自測試電路。我們的內建自我測試電路支援SNN-Test測試演算法，可針對慢積分與快積分錯誤進行測試。根據我們的實驗結果，此內建自我測試電路可對待測電路進行SNN-Test實速測試，且僅增加晶片面積0.8%。

Design for testability (DFT) has always played a very important role in improving the quality and reliability of very large-scale integrated-circuit (VLSI) and semiconductor memories. Among the various DFT methods, the built-in self-test (BIST) is effective and essential for embedded memories. The traditional testing method relies on automatic test equipment (ATE) for transmitting the test vectors and monitoring the test responses. However, transmitting test vectors to, and receiving responses from the embedded memories on the die under test (DUT) will need to consider the extra signal delay of the ATE, the load board, the package pins, the input and output (IO) pads, and the interconnections between the IO pads and the memory cores. Therefore, the clock frequency for testing cannot reach the speed of the actual operation of the memories, and there may be extra IO pads and routing area to support ATE testing of on-chip memories. The on-chip BIST circuit can directly generate and send test vectors to, and receive response vectors from the memory under test, i.e., the at-speed test can be done. In recent years, memristors have been considered suitable for implementing the synapses in spiking neural networks (SNNs). In addition to storing the synaptic weights, memristors can also implement the multiplication and addition computation of weights. The memristor-based SNN architectures potentially can improve the energy efficiency of the SNN computation. In previous work from our lab, the functional fault modules for SNNs have been proposed, i.e., the slow integration fault (SIF) and fast integration fault (FIF) models [3]. A test algorithm for memristor-based SNN has also been proposed, which is called the SNN-Test. In this work, we develop a BIST scheme that implements the SNN-Test. Experimental results show that our BIST scheme can perform at-speed testing of the SNN, and covers all the SIFs and FIFs, with only about 0.8% of silicon area overhead.

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