本論文提出一個應用於單導程心電訊號分析之具有多端輸入特性一維卷積神經網路硬體加速器，可以針對正常心跳、心房早期收縮(Atrial Premature Contraction, APC)、心室早期收縮(Premature Ventricular Contraction, PVC)作偵測辨識。隨著人工智慧(Artificial Intelligence, AI)的崛起，深度學習常被應用於疾病辨識中，其中以卷積神經網路(Convolution Neural Network, CNN)最為著名，藉由海量的心電資料庫進行單一視窗之模型訓練。然而，特定疾病並無法藉由單一心跳辨別，因此本論文添加兩種生醫領域重視的參數作為特徵值，改善傳統卷積網路架構所面臨的弊端。
本論文的演算法流程可分為三個部分，分別是資料彙總與視窗化處理、訊號預處理、一維卷積神經網路模型分類器。首先，將資料庫數據以R波為中心，建構出共計300點的原始資料(Raw Data)，接著針對各視窗進行自動化標籤(Label)。第二部分則是將視窗化數據進行預處理(Preprocessing)，最後一部分是神經網路的訓練，將訓練資料透過卷積層進行特徵萃取(Feature Extraction)並交由全連接層進行分類，輸出辨識結果。此外，根據總參數量(Parameter)、總乘法運算量(Multiplication Operator)設計出具有高準確度之輕量化模型。關於硬體實現之部分，使用資料再利用技術減少數據於記憶體階層間傳遞，大幅降低功耗和減少硬體面積。
本論文將此架構分別實現於軟體演算法及硬體演算法上，其中應用於軟體演算法部分，尚未添加任何特徵值，其準確率為97.31%；添加特徵值後，準確率提高至98.43%。硬體演算法部分，經量化處理後採用16Q6格式，並在架構上使用Convolution Data Reuse及FC parallel Neuron減少從記憶體反覆讀取之消耗，最終硬體準確率為97.62%。驗證部分使用FPGA Xilinx PYNQ Z2開發板，本架構共使用1257個查找表(LUT)、1177個暫存器(FF)、13個乘法器單元(DSP)、6個I/O port，以及BRAM總容量為9KB，進行分類運算之運行時間(Run Time)為2.4465ms、功耗0.107W、量能(Energy-Efficiency)為96.08 (MOPS/W)。結果顯示所提之架構為高量能(High Throughput and High Energy-Efficiency)且確實能應用於單導程心電訊號之疾病辨識。

In this work, a hardware accelerator for one-dimensional convolutional neural network with multi-input characteristics for single-lead electrocardiogram analysis has been proposed, which can detect and classify normal heartbeats, atrial premature contractions (APCs), and premature ventricular contractions (PVCs). However, specific diseases cannot be identified through a single heartbeat, so we add two biomedical parameters as features to improve the drawbacks faced by traditional convolutional neural network structures. The standards for feature selection are also provided. With the optimization of the total number of parameters and multiplication operators, a lightweight model with high accuracy and low parameter has been designed. The MIT-BIH Arrhythmia Database[3] is used that contains 48 half-hour ECG signals recorded from different patients and marked by at least two doctors. The accuracy of software simulation is 97.31% without adding any features, and it increases to 98.43% after adding features. The DLA is implemented on Xilinx PYNQ-Z2 FPGA board. The latency is 2.4465ms during classification. The total power consumption is 0.107W in 1MHz operation frequency. The energy-efficiency is 96.08 (MOPS/W), and the accuracy can achieve 97.62% with the 16Q6 format quantization.

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