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研究生： 陳彥錡
Chen, Yen-Chi
論文名稱： 一個具有雙方向頻率偵測並操作於0.5 Gbps至5Gbps連續頻率時脈與資料回復電路
A 0.5-to-5 Gbps Continuous Rate Clock and Data Recovery Circuit with Bi-directional Frequency Detection
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 77
中文關鍵詞： 資料時脈回復電路 、頻率偵測 、雙方向頻率偵測
外文關鍵詞： clock and data recovery, frequency acquisition, bi-directional frequency detection
相關次數： 點閱：113  下載：1 
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    • 在本論文中提出了一個操作在連續頻率並具有雙方向性頻率偵測資料時脈回復電路。此電路設計的主要原理是結合旋轉式頻率偵測以及次諧波頻率偵測的技巧，來達到較寬操作頻率以及具有雙方向頻率偵測的特性，並進而實現一個時脈資料回復電路。
    驗證論文所提方法的資料時脈回復電路晶片以台灣積體電路公司所提供的0.18-µm製程進行設計。晶片核心面積為0.137 mm2。實測結果顯示，操作在輸入資料頻率為0.5 Gbps下，回復時脈的抖動均方根值以及峰對峰值分別為15.9 ps以及107.5 ps，功率消耗為121.1 mW。當操作在輸入資料頻率為4 Gbps下，回復時脈的抖動均方根值以及峰對峰值分別為17.3 ps以及92.5 ps，功率消耗為132.1 mW。

    This thesis presents a continuous rate clock and data recovery circuit with bi-directional frequency detection. In this work, rotational frequency detector and sub-harmonic tone detection technique are combined to widen the frequency range accompanied with bi-directional detection characteristic that is desirable in wide range operation. Based on the proposed frequency detection methodology, a proof-of-concept clock and data recovery circuit is implemented.
    The clock and data recovery circuit is fabricated in a TSMC 0.18-µm CMOS process. The core area is 0.137 mm2. The power consumption of this CDR circuit is 121.1 mW for a supply of 1.8V when input data rate is 0.5 Gbps. The root-mean-square (RMS) jitter of recovered clock is 15.9 ps and peak-to-peak (p-p) jitter of recovered clock is 107.5 ps. Moreover, when input data rate is 4 Gbps, the RMS jitter of recovered clock is 17.3 ps and p-p jitter of recovered clock is 92.5 ps. The power consumption is 132.1 mW.

    Chapter 1 Introduction 1 1.1 WIRELINE COMMUNICATION 1 1.2 THESIS ORGANIZATION 2 Chapter 2 Basics of Clock and Data Recovery Circuits 2.1 FIBER-OPTICS COMMUNICATION 3 2.2 BASICS OF PLL-BASED CLOCK AND DATA RECOVERY CIRCUITS 5 2.2.1 Phase Detector 6 2.2.2 Frequency Detector 9 2.2.3 PLL-Based CDR Circuit 16 2.2.4 Reference less CDR Circuit 18 2.3 PERFORMANCE METRIC OF CLOCK AND DATA RECOVERY CIRCUITS 19 2.4 WIDE RANGE CONTINUOUS RATE CLOCK AND DATA RECOVERY CIRCUITS 22 2.4.1 A 155.52Mbps to 3.125Gbps Continuous Rate Clock and Data Recovery Circuit 22 2.4.2 A 180Mbps to 3.2Gbps, Continuous Rate, Fast Locking CDR without Using External Reference Clock 24 2.4.3 A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Duty-Cycle Error Tolerance 25 2.4.4 A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit with a Bidirectional Frequency Detector 26 Chapter 3 Proposed Architecture of CDR and Circuit Design 28 3.1 BRIEF INTRODUCTION 28 3.2 CIRCUIT DESCRIPTION 29 3.2.1 PROPOSED FREQUENCY DETECTION METHOD 29 3.2.2 WIDE RANGE VOLTAGE CONTROLLED OSCILLATOR 32 3.2.3 PHASE DETECTOR AND VI CONVERTER 36 3.2.4 ANALOG AND DIGITAL COMPARATORS 37 3.2.5 BAND SELECTION CIRCUIT 41 3.2.6 LOOP FILTER 42 3.2.7 CURRENT MODE LOGIC 43 3.2.8 OUPUT BUFFER/INPUT MATCHING 45 3.3 PROPOSED CDR ARCHITECTURE 46 3.4 LAYOUT AND FLOOR PLAN 49 Chapter 4 Simulation and Measurement Results 52 4.1 THE SIMULATION OF WIDE RANGE VCO 52 4.1.1 Post-simulation 53 4.1.2 Testing setup and measured results 64 Chapter 5 Conclusions and Future Work 72 Bibliography 74

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