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研究生： 許宏銘
Hsu, Hung-Min
論文名稱： 全關聯式資料快取記憶體之軟體測試方法
Software-Based Test Methodology for Fully Associative Data Cache
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 英文
論文頁數： 67
中文關鍵詞： 軟體測試方法 、全關聯式資料快取記憶體
外文關鍵詞： fully associative data cache, software-based test methodology
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    • 過去在測試處理器中的快取記憶體上，常會使用內建式自我測試或是可測試設計的技術來測試快取記憶體中的記憶體和控制邏輯。然而這些技術會在電路中加上測試用的電路，影響到快取記憶體的效能，所以有一種無傷害(non-intrusive)的測試方式「軟體測試方法」被提出來解決快取記憶體測試的問題。軟體測試方法是使用處理器內部自有的元件和指令集來測試快取記憶體，不需要加入額外測試的電路或是修改處理器的設計，因此能在不影響快取記憶體原本的效能下，達到良好的測試品質，所以特別適用於高效能的處理器。過去在文獻上所提出的對快取記憶體的軟體測試方法大多只針對直接映射(direct-mapped)或是集合關連(set associative)的快取記憶體，而鮮少去探討對全關聯式(fully associative)快取記憶體的軟體測試方法。在本論文中，我們針對全關聯式資料快取記憶體中的主要元件，包括記憶體和控制邏輯，提出其軟體測試方法。在記憶體部分，以前並無人討論過內容可定址記憶體(content-addressable memory)的相關軟體測試。在本論文中我們完整地討論如何用軟體的方式去測試內容可定址記憶體，並且提出了一個可以達到很高錯誤涵蓋率的軟體測試方法。而對全關聯式資料快取記憶體中的控制邏輯，我們提出了一個系統化的方式來產生功能性的測試序列，這些功能性的測試序列是針對快取記憶體中的許多功能而開發，包括快取記憶體的基本控制功能以及許多的特殊功能，故為一相當完整之控制邏輯測試序列。

    The testing problem of caches in a processor may be addressed using the built-in self-test (BIST) or design-for-test (DFT) techniques. However, the insertion of test circuits required by these techniques would adversely affect the performance of the cache. Hence, the software-based test methodology which uses processor resources to self test the components in the processor is often used for high performance consideration. Previous software-based test schemes mainly deal with the direct-mapped and set associative caches. The testing of the fully associative data cache has seldom been discussed. In this thesis, we propose a novel software-based test methodology for both memory arrays and control logic in the fully associative data cache. For the memory arrays, our main focus is on the content-addressable memory (CAM) that have been used as the tag RAM of the cache and its software-based test issue has not been addressed previously. We shall propose a software-based test method that can achieve very high test quality for the CAM. For the control logic, a systematic approach to develop functional test sequences for various cache functions is proposed. The developed test sequences are shown to be able to comprehensively test the control logic in a fully associative data cache.

    Abstract Chapter 1 Introduction ........................................................................ P1 1.1 Motivation ..................................................................................................... P1 1.2 Overview of Thesis ....................................................................................... P2 1.3 Organization of Thesis .................................................................................. P4 Chapter 2 Background and Previous Work ....................................... P6 2.1 Background ................................................................................................... P6 2.1.1 Fully associative data cache .................................................................. P6 2.1.2 CAM structure and its fault models ...................................................... P9 2.1.3 Data background ................................................................................... P11 2.1.4 Special cache functions ......................................................................... P12 2.1.5 Address and instruction notations ......................................................... P13 2.2 Previous Work ............................................................................................... P16 2.2.1 Software-based test methodology for memories in the cache ........... P16 2.2.2 Software-based test methodology for control logic in the cache .......... P17 2.2.3 CAM test algorithms ............................................................................. P17 Chapter 3 Tag Memory (CAM) Testability Analysis & Enhancement 3.1 Read Capability ............................................................................................. P18 3.2 Write Capability ............................................................................................ P19 3.2.1 Ascending and descending addressing order ..................................... P19 3.2.2 Multiple write operations on a word ..................................................... P21 3.2.3 Data background ................................................................................... P22 Chapter 4 Software-Based Test for Tag Memory (CAM) ................. P23 4.1 Overview of Proposed Software-Based Test Procedure................................ P23 4.2 New CAM Test Algorithm: SW March C .................................................... P24 4.2.1 SW March C algorithm ........................................................................ P25 4.2.2 Theoretical analysis .............................................................................. P28 4.3 Integration of Comparison Fault Test to SW March C ................................. P30 4.3.1 Requirement to detect comparison fault ............................................... P30 4.3.2 Analysis of SW March C on detecting comparison faults .................... P30 4.3.3 Enhanced SW March C: SW March C+ ............................................... P31 4.3.4 Theoretical analysis .............................................................................. P34 4.4 Multiple Data Background Sets for SW March C and C+ ........................... P34 4.4.1 Generation of single data background set ............................................ P34 4.4.2 Generation of multiple data background sets ....................................... P35 4.5 Transformation of SW March C+ to Test Instructions .................................. P37 4.5.1 Test operations in SW March C+ .......................................................... P37 4.5.2 Guidelines to develop instruction mappings ......................................... P38 4.5.3 Test instruction mappings ..................................................................... P38 4.5.4 Ascending and descending addressing order ........................................ P40 Chapter 5 Software-Based Test for Control Logic ............................. P42 5.1 A Systematic Approach to Develop Functional Test Sequence .................... P42 5.2 Developed Functional Test Sequences .......................................................... P46 5.2.1 Write policy ........................................................................................... P46 5.2.2 Replacement algorithm ......................................................................... P48 5.2.3 Special cache function .......................................................................... P48 Chapter 6 Experimental Results .......................................................... P51 6.1 CAM Fault Simulator ................................................................................... P51 6.2 Case Study: ARM922T Data Cache ............................................................. P53 6.2.1 Data cache in ARM922T ...................................................................... P53 6.2.2 Ascending and descending addressing order ........................................ P54 6.2.3 Test results of data memory .................................................................. P56 6.2.4 Test results of tag memory (CAM) ....................................................... P57 6.3 Discussion .................................................................................................... P58 6.3.1 Processor architecture ............................................................................. P58 6.3.2 CAM size ................................................................................................ P59 Chapter 7 Conclusions .......................................................................... P61 Reference .................................................................................................. P64

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