在以能量消耗考量為主的應用中，如可攜式行動裝置、生醫電子系統、以及無線感測器等，將電路操作於次臨界電壓區域為有效降低能量消耗的有效方法之一。然而，將電路操作於次臨界電壓區域會嚴重的降低電晶體驅動電流對漏電流的比值，更增加對製程變異的敏感度，使得電路的強健性下降，導致電路功能容易錯誤，因此為了增加電路操作於次臨界電壓區域的強健性，本論文提出了N傾向型的史密特觸發架構，此架構不僅可以有效的增加邏輯電路驅動電流對漏電流的比值，更可以降低對製程變異的敏感度，使得電路在次臨界電壓區域可以穩定的操作。本論文所提出的架構與史密特觸發邏輯架構[1]在驗證電路乘法累加器中，以台積電90奈米製程做後佈局模擬後的比較，在操作電壓0.2V時，改善6倍的時間能量積並減少40%的面積。

Sub-threshold operation has been shown to be a promising approach for ultra-low power applications, such as portable mobile devices, biomedical electronic systems and wireless sensor network. However, operating logic circuits in the sub-threshold regime would seriously degrade the ratio of transistor driving current to leakage current and increase the sensitivity of process variations, thus increasing the possibility of logic functional failures. To increase the robustness of logic circuit in the sub-threshold regime, we propose a sub-threshold logic style called N-Critical Schmitt-Trigger logic. This structure could not only effectively increase the ratio of logic circuit driving current to leakage current, but also reduce the sensitivity of process variation when operated in the sub-threshold regime. In this thesis, the multiplier and accumulator (MAC) circuits are implemented in TSMC 90nm to demonstrate the feasibility of our proposed N-critical Schmitt-Trigger logic in the sub-threshold regime. According to post-layout simulation results, the MAC circuit implemented with our proposed logic structure shows 40% area overhead reduction and 6x energy-delay-product (EDP) improvement at 0.2V when compared with conventional Schmitt-Trigger logic structure[1].

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