本論文提出了逐漸趨近式類比數位轉換器的快速位元錯誤率估計方法和改良之測試技術。
我們分析了逐漸趨近式類比數位轉換器中產生位元錯誤的主要來源，包括比較器雜訊、比較器的亞穩態和邏輯電路錯誤，以了解位元錯誤之產生機制及其效應。基於分析的結果，我們建立位元錯誤率之數學模型，並以軟體實現此數學模型，據以估計逐漸趨近式類比數位轉換器的位元錯誤率(BER)。與傳統基於模擬器的估計方式相比，本論文所提出之估計方法可以在短時間內準確地估計逐漸趨近式類比數位轉換器的位元錯誤率。此外，我們還指出了傳統上用於測量逐漸趨近式類比數位轉換器之位元錯誤率的測試機制問題，提出了一種基於傳統測試機制的後處理方法，將測量到的位元錯誤率修改為正確的數值。
為了驗證所提出之估計方法和後處理方法的準確性，我們以台積電40奈米CMOS標準1P9M製程實作逐漸趨近式類比數位轉換器之晶片。其核心面積為 0.0204 mm2。在0.9伏特電源供應及每秒一億兩千五百萬次的取樣頻率下，奈奎斯特輸入頻率下的有效位元為9.1位元。基於模擬的結果，本作品所測量到之位元錯誤率位於合理的區間，且其數值對取樣速率的改變趨勢也符合預測結果。

A quick bit error rate estimation method and a modified test technique for SAR ADCs are presented in this thesis.
We analyze the major sources that would result in bit errors, including the comparator noise, the comparator metastability, and the logic circuit fault, to understand the causes and effects of the bit errors in SAR ADCs. Based on the analysis, we construct a mathematic model, and implement a mathematical tool based on the model, to estimate the bit error rate (BER) of SAR ADCs. The proposed estimation method can estimate the BER of SAR ADCs accurately in a short time compared with the conventional simulator-based estimation method. In addition, we also point out a problem of the conventional test scheme used to measure the BER of SAR ADCs. A post-processing method based on the conventional test scheme is proposed to modify the measured BER to be a more correct one.
A SAR ADC chip was fabricated in a TSMC 40-nm CMOS technology to verify the effectiveness of the proposed estimation method and the post-processing method. The core area occupies 0.0204 mm2. At a supply voltage of 0.9-V and sampling rate of 125-MS/s, the ENOB with input frequency near Nyquist frequency is 9.1 bits. Based on the simulation and measurement results, the BERs estimated by the proposed method locate within the reasonable region and the tendency of the BER value versus the sampling rate also fits to the estimated results.

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