成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	張佑瑜 Chang, You-Yu
論文名稱：	透過限制單元分佈範圍和調整繞線權重達成以時序為導向之數學解析全域擺置 A Timing-driven Analytical Global Placement by Restricting Cell Distribution Range and Adjusting Net Weights
指導教授：	林家民 Lin, Jai-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	112
語文別：	英文
論文頁數：	30
中文關鍵詞：	時序、多階層架構、實體設計、擺置
外文關鍵詞：	timing, multilevel framework, physical design, placement
相關次數：	點閱：76 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

摘要 i
Abstract ii
誌謝 iii
Table of Contents iv
List of Tables vi
List of Figures vii
Chapter 1 Introduction 1
1.1 Motivation 2
1.2 Our Contribution 4
Chapter 2 Preliminaries 6
2.1 Net Weighting-based Analytical Placement Formulation 6
2.2 Historical Net Weight Adjustment Function 7
Chapter 3 New Analytical Placement Algorithm 8
3.1 Overview of Our Methodology 8
3.2 Pin-connectivity-aware Score Function 9
Chapter 4 Expected Distribution Range in The Analytical Placement 12
4.1 Preliminaries 12
4.2 Procedure to Determine Expected Distribution Ranges of Objects 15
4.3 Maximum Placeable Area of Each Bin in a Diffusion Region 17
Chapter 5 Timing-Driven Global Placement Algorithm 19
5.1 Overview for Our TDP Algorithm 19
5.2 Calculation of Net Weights 21
5.3 Net Weight Adjustment Considering Historical Value 22
Chapter 6 Experimental Results 23
6.1 Effect of Improved Analytical Placement Approach with Respect to Classic Analytical Placement Approach 23
6.2 Comparison with Other Timing-driven Placers 25
Chapter 7 Conclusion 27
Bibliography 28
                                    

[1] C. Alpert, A. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia, “A semi-persistent clustering technique for VLSI circuit placement,” in Proc. of ISPD, pp. 200-207, 2005.
[2] M. Burstein and M. N. Youssef, “Timing Influenced Layout Design,” in Proc. of DAC, pp. 124-130, 1985.
[3] H. Chang, E. Shragowitz, J. Liu, H. Youssef, B. Lu, and S. Sutanthavibul, “Net criticality revisited: An effective method to improve timing in physical design,” in Proc. of ISPD, pp. 155–160, 2002.
[4] A. Chowdhary et al., “How accurately can we model timing in a placement engine?,” in Proc. of DAC, pp. 801-806, 2005.
[5] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang,“NTUplace3: An analytical placer for large-scale mixed-size designs with pre-placed blocks and density constraints,” IEEE Trans. of TCAD, vol. 27, no. 7, pp. 1228-1240, 2008.
[6] A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. Jukl, P. Kozak, and M. Wiesel, “Chip layout optimization using critical path weighting,” in Proc. of DAC, pp. 133-136, 1984.
[7] H. Eisenmann and F. M. Johannes, “Generic global placement and floorplanning,” in Proc. of DAC, pp. 269-274, 1998.
[8] Zizheng Guo and Yibo Lin. 2022. “Differentiable-timing-driven global placement,” in Proc. of DAC, pp. 1315-1320, 2022.
[9] T. Hamada, C.-K. Cheng, and P. M. Chau, “Prime: A timing-driven placement tool using a piecewise linear resistive network approach,” in Proc. of DAC, pp. 531–536, 1993.
[10] B. Halpin, C. R. Chen, and N. Sehgal, “A sensitivity based placer for standard cells,” in Proc. of GLSVLSI, pp. 193–196, 2000.
[11] M.-K. Hsu, V. Balabanov and Y. -W. Chang, “TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average Wirelength Model,” IEEE Trans. of TCAD, vol. 32, no. 4, pp. 497-509, 2013.
[12] T.-W. Huang and M. D. F. Wong, “OpenTimer: A high-performance timing analysis tool,” in Proc. of ICCAD, pp. 895-902, 2015.
[13] M. A. B. Jackson and E. S. Kuh, “Performance-driven placement of cell based IC’s,” in Proc. of DAC, pp. 370-375, 1989.
[14] T. Kong, “A novel net weighting algorithm for timing-driven placement, ” in Proc. of ICCAD, pp. 172-176, 2002.
[15] A. B. Kahng and Qinke Wang, “Implementation and extensibility of an analytic placer,” IEEE Trans. of TCAD, vol. 24, no. 5, pp. 734-747, 2005.
[16] M.-C. Kim, J. Hu, J. Li and N. Viswanathan, “ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite,” in Proc. of ICCAD, pp. 921-926, 2015.
[17] J.-M. Lin, S.-T. Li, and Y.-T. Wang, “Routability-driven mixed-size placement prototyping approach considering design hierarchy and indirect connectivity between macros,” in Proc. of DAC, pp. 1-6, 2019.
[18] P. Liao, S. Liu, Z. Chen, W. Lv, Y. Lin and B. Yu, “DREAMPlace 4.0: Timing-driven global placement with momentum-based net weighting,” in Proc. of DATE, pp. 939-944, 2022.
[19] J.-M. Lin, Y.-Y. Chang and W.-L. Huang “Timing-Driven Analytical Placement According to Expected Cell Distribution Range,” to be appeared in Proc. of ACM International Symposium on Physical Design (ISPD), 2024.
[20] W. C. Naylor, R. Donelly, and L. Sha, “Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer,” U.S. Patent 6 301 693, Oct 9, 2001.
[21] B. Obermeier and F. M. Johannes, “Quadratic placement using an improved timing model,” in Proc. of DAC, pp. 705–710, 2004.
[22] B. M. Riess and G. G. Ettelt, “SPEED: Fast and efficient timing driven placement,” in Proc. of ISCAS, pp. 377-380, 1995.
[23] W. Swartz and C. Sechen, “Timing driven placement for large standard cell circuits,” in Proc. of DAC, pp. 211–215, 1995.
[24] Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen,“Sensitivity guided net weighting for placement driven synthesis,” in Proc. of ISPD, pp. 124–131, 2004.
[25] Z. Xiu and R. A. Rutenbar, “Timing-driven placement by grid-warping,” in Proc. of DAC, pp. 585–591, 2005.
[26] Cadence, Inc. Innovus. Accessed: November 23, 2020. [Online]. Available: https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/innovus-implementation-system.html
[27] Himax Technologies, Inc. Available: https://www.himax.com.tw/zh/company/about-himax/
[28] Synopsys, Inc. IC Compiler II Accessed: July 1, 2022. [Online]. Available: https://www.synopsys.com/implementation-and-signoff/physical-implementation/ic-compiler.html

校內：2028-11-15公開
校外：2028-11-15公開電子論文尚未授權公開，紙本請查館藏目錄

簡易檢索 / 詳目顯示

相關論文